mux.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 29 行

use work.synopsys.all;

entity MUX is
	port(ALARM_HRS,TIME_HRS : in  INTEGER range 1 to 12;
       	     ALARM_MINS,TIME_MINS :in  INTEGER range 0 to 59; 
	     ALARM_AM_PM,TIME_AM_PM : in BIT;
	     ALARM_SET :in BIT;
	     OUTBUS :out unsigned(10 downto 0));
end;

architecture behavior of MUX is
begin

	process(ALARM_SET,ALARM_HRS,TIME_HRS,ALARM_MINS,
		TIME_MINS,ALARM_AM_PM,TIME_AM_PM)
	
	variable temp : unsigned(10 downto 0);
	
	begin
		if (ALARM_SET = '1') then
		   temp := conv_unsigned(ALARM_HRS,4)&conv_unsigned(ALARM_MINS,6)&ALARM_AM_PM;
		   else 
		 	temp := conv_unsigned(TIME_HRS,4)&conv_unsigned(TIME_MINS,6)&TIME_AM_PM;
		end if;

		OUTBUS <= temp;
	end process;
end;