hours_filter.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 20 行

entity HOURS_FILTER is
    port (TENS_DIGIT_HOURS_IN : in BIT_VECTOR (6 downto 0);
	  TENS_DIGIT_HOURS_OUT : out BIT_VECTOR (6 downto 0));
end;

architecture BEHAVIOR of HOURS_FILTER is
begin

   process (TENS_DIGIT_HOURS_IN)
   begin
     if TENS_DIGIT_HOURS_IN = "1111110" then
	TENS_DIGIT_HOURS_OUT <= "0000000";
     else
	TENS_DIGIT_HOURS_OUT <= TENS_DIGIT_HOURS_IN;
     end if;
   end process;

end BEHAVIOR;