comparator.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 23 行

entity COMPARATOR is
    port (ALARM_HRS,CLOCK_HRS :in  INTEGER range 1 to 12; 
          ALARM_MINS,CLOCK_MINS : in  INTEGER range 0 to 59;
	  ALARM_AM_PM, CLOCK_AM_PM: in BIT;
	  RINGER: out BIT);
end;

architecture BEHAVIOR of COMPARATOR is
begin

   COMP:process(ALARM_HRS,CLOCK_HRS,ALARM_MINS,CLOCK_MINS,ALARM_AM_PM,CLOCK_AM_PM)
   begin
	RINGER <= '0';
	if ((ALARM_HRS = CLOCK_HRS) and (ALARM_MINS = CLOCK_MINS) and 
           (ALARM_AM_PM = CLOCK_AM_PM))  then
		RINGER <= '1';
	 end if;

   end process;

end BEHAVIOR;