convertor_ckt.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 34 行

use work.synopsys.all;

entity CONVERTOR_CKT is 
	port (connect13 : in unsigned(9 downto 0);
              disp1,disp2 : out BIT_VECTOR(13 downto 0));
end;

architecture BEHAVIOR of CONVERTOR_CKT is
	component CONVERTOR
	port(T0,T1,T2,T3,T4,T5: in BIT ;
             A0,B0,C0,D0,E0,F0,G0,A1,B1,C1,D1,E1,F1,G1: out BIT);
	end component;

	component HOURS_FILTER 
	port(TENS_DIGIT_HOURS_IN: in BIT_VECTOR(6 downto 0);
	     TENS_DIGIT_HOURS_OUT:out BIT_VECTOR(6 downto 0));
	end component;

	signal connect14 : BIT_VECTOR(13 downto 0);
	signal data_in1 : unsigned(5 downto 0);
	signal data_out1 : BIT_VECTOR(6 downto 0);

	begin
		data_in1 <= '0'&'0'&connect13(9 downto 6);
 		disp1 <= connect14(13 downto 7)&data_out1;
	
 		U7: CONVERTOR port map(data_in1(5),data_in1(4),data_in1(3),data_in1(2),data_in1(1),data_in1(0),connect14(13),connect14(12),connect14(11),connect14(10),connect14(9),connect14(8),connect14(7),connect14(6),connect14(5),connect14(4),connect14(3),connect14(2),connect14(1),connect14(0)); 
		U8: CONVERTOR port map(connect13(5),connect13(4),connect13(3),connect13(2),connect13(1),connect13(0),disp2(13),disp2(12),disp2(11),disp2(10),disp2(9),disp2(8),disp2(7),disp2(6),disp2(5),disp2(4),disp2(3),disp2(2),disp2(1),disp2(0));
		U9: HOURS_FILTER port map(connect14(6 downto 0),data_out1);
end;