comparator.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 20 行

module COMPARATOR(ALARM_HRS,CLOCK_HRS,ALARM_MINS,CLOCK_MINS,ALARM_AM_PM, 
                  CLOCK_AM_PM,RINGER);
input [3:0] ALARM_HRS,CLOCK_HRS;
input [5:0] ALARM_MINS,CLOCK_MINS;
input ALARM_AM_PM, CLOCK_AM_PM;
output RINGER;
reg RINGER;

     always @ (ALARM_HRS or CLOCK_HRS or ALARM_MINS or CLOCK_MINS or 
               ALARM_AM_PM or CLOCK_AM_PM)  begin
	    RINGER = 1'b0;
	if ((ALARM_HRS == CLOCK_HRS) &&  (ALARM_MINS == CLOCK_MINS) && 
           (ALARM_AM_PM == CLOCK_AM_PM)) 
		RINGER = 1'b1;
	 end 

endmodule