time_block.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 19 行

module TIME_BLOCK ( SET_TIME, HRS, MINS, CLK, CONNECT6, 
     CONNECT7,
     CONNECT8 );
input  SET_TIME, HRS, MINS, CLK;
output [3:0] CONNECT6;
output [5:0] CONNECT7;
output  CONNECT8;
    wire CONNECT3, CONNECT4, CONNECT5;
    TIME_STATE_MACHINE U1 ( .TIME_BUTTON(SET_TIME), .HOURS_BUTTON(HRS), 
        .MINUTES_BUTTON(MINS), .CLK(CLK), .SECS(CONNECT5), .HOURS(CONNECT3), 
        .MINS(CONNECT4) );
    TIME_COUNTER U2 ( .SECS(CONNECT5), .HOURS(CONNECT3), .MINS(CONNECT4), 
        .CLK(CLK), .HOURS_OUT(CONNECT6),
        .MINUTES_OUT(CONNECT7) , 
        .AM_PM_OUT(CONNECT8) );
endmodule