hours_filter.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 15 行

module HOURS_FILTER (TENS_DIGIT_HOURS_IN, TENS_DIGIT_HOURS_OUT);
input  [6:0] TENS_DIGIT_HOURS_IN;
output [6:0] TENS_DIGIT_HOURS_OUT;

reg [6:0] TENS_DIGIT_HOURS_OUT;

always @ (TENS_DIGIT_HOURS_IN)
   if (TENS_DIGIT_HOURS_IN == 7'b1111110)
      TENS_DIGIT_HOURS_OUT = 7'b0000000;
   else
      TENS_DIGIT_HOURS_OUT = TENS_DIGIT_HOURS_IN;

endmodule