time_counter.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 74 行

module TIME_COUNTER (HOURS, MINS, SECS, CLK, HOURS_OUT, MINUTES_OUT, AM_PM_OUT);
input HOURS, MINS, SECS, CLK;
output [3:0] HOURS_OUT;
output [5:0] MINUTES_OUT;
output AM_PM_OUT;

reg [3:0] HOURS_OUT;
reg [5:0] MINUTES_OUT;
reg [5:0] CURRENT_SECS;
reg AM_PM_OUT;

always @ (posedge CLK)
begin

    MINUTES_OUT = MINUTES_OUT;
    HOURS_OUT = HOURS_OUT;
    AM_PM_OUT = AM_PM_OUT;
    CURRENT_SECS = CURRENT_SECS;

    if (SECS & !MINS & !HOURS)
       begin
       if (CURRENT_SECS == 6'd59)
	  begin
	  CURRENT_SECS = 6'd0;
	  if (MINUTES_OUT == 6'd59)
	     begin
	     MINUTES_OUT = 6'd0;
	     if (HOURS_OUT == 4'd12)
		begin
		HOURS_OUT = 4'd1;
		AM_PM_OUT = !AM_PM_OUT;
		end
	     else
		HOURS_OUT = HOURS_OUT + 1'd1;
	     end
	  else
	     MINUTES_OUT = MINUTES_OUT + 1'd1;
	  end
       else
	  CURRENT_SECS = CURRENT_SECS + 1'd1;
       end
    else if (!SECS & MINS & !HOURS)
       begin
       CURRENT_SECS = 6'd0;
       if (MINUTES_OUT == 6'd59)
	  begin
	  MINUTES_OUT = 6'd0;
	  if (HOURS_OUT == 4'd12)
	     begin
	     HOURS_OUT = 4'd1;
	     AM_PM_OUT = !AM_PM_OUT;
	     end
	  else
	     HOURS_OUT = HOURS_OUT + 1'd1;
	  end
       else
	  MINUTES_OUT = MINUTES_OUT + 1'd1;
       end
    else if (!SECS & !MINS & HOURS)
       begin
       CURRENT_SECS = 6'd0;	
       if (HOURS_OUT == 4'd12)
	  begin
	  HOURS_OUT = 4'd1;
	  AM_PM_OUT = !AM_PM_OUT;
	  end
       else
	  HOURS_OUT = HOURS_OUT + 1'd1;
       end
       
end

endmodule