analyzres.tcl

design compile synthesis user guide

#
# Tcl script file for Chapter 10
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# Remove any designs in memory
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remove_design -all
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# Read in the compiled design
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read_file -format db [list {./db/TOP_compiled.db}]
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# Generate report
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report_bus
report_cell
report_net
report_compile_options
report_hierarchy
report_timing -path full -delay max -max_paths 3 -nworst 1
current_instance {U1/U1}
report_timing -path full -delay max -max_paths 3 -nworst 1
current_instance {../..}
report_timing -path end -delay max -max_paths 10 -nworst 1
#
# Turn on the pin_name_layer
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set_layer pin_name_layer visible TRUE
set_layer pin_name_layer line_width 1
set_layer pin_name_layer plot_line_width 0
set_layer pin_name_layer red 65535
set_layer pin_name_layer green 65535
set_layer pin_name_layer blue 65535
#
# Show timing to a specific pin
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report_timing -path full -delay max -max_paths 10 -nworst 1 -from [find pin [list {U4/CLOCK_AM_PM}]] -to [find pin [list {U5/COMPARE_IN}]]
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# Set current_design to CONVERTOR_0
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current_instance {U4}
current_instance {../U5}
current_instance {..}
current_design {TOP_compiled.db:CONVERTOR_0}
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# Perform a check_design and check_timing on design TOP
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current_design {TOP_compiled.db:TOP}
check_design
check_timing
#
quit