optgoals.tcl

design compile synthesis user guide

#
# Tcl script file for Chapter 8
#
# Remove any designs in memory
#
remove_design -all
#
# Read in the design with attributes set from Chapter 7
#
read_file -format db [list {./db/TOP_attributes.db}]
#
# Create a clock object, then set a clock constraint
#
create_clock -name CLK -period 25 -waveform [list 0 12.5] [list CLK]
#
# Set a delay constraint on the output ports
#
set_output_delay -clock CLK -max -rise 5 {SPEAKER_OUT}
set_output_delay -clock CLK -max -fall 5 {SPEAKER_OUT}
set_output_delay -clock CLK -max -rise 5 {AM_PM_DISPLAY}
set_output_delay -clock CLK -max -fall 5 {AM_PM_DISPLAY}
set_output_delay -clock CLK -max -rise 5 {DISP2[13]}
set_output_delay -clock CLK -max -fall 5 {DISP2[13]}
set_output_delay -clock CLK -max -rise 5 {DISP2[12]}
set_output_delay -clock CLK -max -fall 5 {DISP2[12]}
set_output_delay -clock CLK -max -rise 5 {DISP2[11]}
set_output_delay -clock CLK -max -fall 5 {DISP2[11]}
set_output_delay -clock CLK -max -rise 5 {DISP2[10]}
set_output_delay -clock CLK -max -fall 5 {DISP2[10]}
set_output_delay -clock CLK -max -rise 5 {DISP2[9]}
set_output_delay -clock CLK -max -fall 5 {DISP2[9]}
set_output_delay -clock CLK -max -rise 5 {DISP2[8]}
set_output_delay -clock CLK -max -fall 5 {DISP2[8]}
set_output_delay -clock CLK -max -rise 5 {DISP2[7]}
set_output_delay -clock CLK -max -fall 5 {DISP2[7]}
set_output_delay -clock CLK -max -rise 5 {DISP2[6]}
set_output_delay -clock CLK -max -fall 5 {DISP2[6]}
set_output_delay -clock CLK -max -rise 5 {DISP2[5]}
set_output_delay -clock CLK -max -fall 5 {DISP2[5]}
set_output_delay -clock CLK -max -rise 5 {DISP2[4]}
set_output_delay -clock CLK -max -fall 5 {DISP2[4]}
set_output_delay -clock CLK -max -rise 5 {DISP2[3]}
set_output_delay -clock CLK -max -fall 5 {DISP2[3]}
set_output_delay -clock CLK -max -rise 5 {DISP2[2]}
set_output_delay -clock CLK -max -fall 5 {DISP2[2]}
set_output_delay -clock CLK -max -rise 5 {DISP2[1]}
set_output_delay -clock CLK -max -fall 5 {DISP2[1]}
set_output_delay -clock CLK -max -rise 5 {DISP2[0]}
set_output_delay -clock CLK -max -fall 5 {DISP2[0]}
set_output_delay -clock CLK -max -rise 5 {DISP1[13]}
set_output_delay -clock CLK -max -fall 5 {DISP1[13]}
set_output_delay -clock CLK -max -rise 5 {DISP1[12]}
set_output_delay -clock CLK -max -fall 5 {DISP1[12]}
set_output_delay -clock CLK -max -rise 5 {DISP1[11]}
set_output_delay -clock CLK -max -fall 5 {DISP1[11]}
set_output_delay -clock CLK -max -rise 5 {DISP1[10]}
set_output_delay -clock CLK -max -fall 5 {DISP1[10]}
set_output_delay -clock CLK -max -rise 5 {DISP1[9]}
set_output_delay -clock CLK -max -fall 5 {DISP1[9]}
set_output_delay -clock CLK -max -rise 5 {DISP1[8]}
set_output_delay -clock CLK -max -fall 5 {DISP1[8]}
set_output_delay -clock CLK -max -rise 5 {DISP1[7]}
set_output_delay -clock CLK -max -fall 5 {DISP1[7]}
set_output_delay -clock CLK -max -rise 5 {DISP1[6]}
set_output_delay -clock CLK -max -fall 5 {DISP1[6]}
set_output_delay -clock CLK -max -rise 5 {DISP1[5]}
set_output_delay -clock CLK -max -fall 5 {DISP1[5]}
set_output_delay -clock CLK -max -rise 5 {DISP1[4]}
set_output_delay -clock CLK -max -fall 5 {DISP1[4]}
set_output_delay -clock CLK -max -rise 5 {DISP1[3]}
set_output_delay -clock CLK -max -fall 5 {DISP1[3]}
set_output_delay -clock CLK -max -rise 5 {DISP1[2]}
set_output_delay -clock CLK -max -fall 5 {DISP1[2]}
set_output_delay -clock CLK -max -rise 5 {DISP1[1]}
set_output_delay -clock CLK -max -fall 5 {DISP1[1]}
set_output_delay -clock CLK -max -rise 5 {DISP1[0]}
set_output_delay -clock CLK -max -fall 5 {DISP1[0]}
#
# Run check design
#
check_design
check_timing
current_design {TOP_attributes.db:CONVERTOR_CKT}
#
# Show the pin name layer
#
set_layer pin_name_layer visible TRUE
set_layer pin_name_layer line_width 1
set_layer pin_name_layer plot_line_width 0
set_layer pin_name_layer red 65535
set_layer pin_name_layer green 65535
set_layer pin_name_layer blue 65535
current_design {TOP_attributes.db:TOP}
#
# Use uniquify to resolve multiple design instances
#
uniquify
#
# Save the design
#
write -format db -hierarchy -output {./db/TOP_before_compile.db} [list {TOP_attributes.db:TOP}]
#
#Delete designs for the optional exercises
#
remove_design [find design {*}]
#
# Read in TOP_attributes (from Chapter 7)
#
read_file -format db [list {./db/TOP_attributes.db}]
#
# Run check design to recreate the warning message about multiple
# design instances
#
check_design
current_design {TOP_attributes.db:CONVERTOR}
#
# Map design CONVERTOR to gates
#
compile -map_effort medium
set current_design {TOP_attributes.db:CONVERTOR}
#
# Place the dont_touch attribute on design CONVERTOR
#
set_dont_touch {TOP_attributes.db:CONVERTOR}
current_design {TOP_attributes.db:TOP}
#
# Rerun check design
#
check_design
#
# Delete designs to run optional exercise on ungroup
#
remove_design [find design {*}]
#
# Read in TOP_attributes (from Chapter 7)
#
read_file -format db [list {./db/TOP_attributes.db}]
#
# Rerun check design to recreate the warning message on multiple
# design instances
#
check_design
current_design {TOP_attributes.db:CONVERTOR}
#
# Set the ungroup attribute on design CONVERTOR
#
set_ungroup {TOP_attributes.db:CONVERTOR}
#
# Rerun check design
#
set current_design {TOP_attributes.db:TOP}
check_design
#
quit