nm_rules.dcsh

design compile synthesis user guide

/*****************************************************************************

	FILE: nm_rules.dcsh		
	AUTHOR: Bill Krieger - Mar 31, 1992

	ABSTRACT: This file defines the naming rules for a number of CAE
	systems and file formats.  These rules are defined using the
	define_name_rules() command in dc_shell. 

	It is suggested that you cut and paste the rules you desire
	and place them in your .synopsys file.  Once your rules are
	defined, you may also want to set the variable "default_name_rules"
	to make your name rules the default for each dc_shell session. 

	You can modify these rules if they do not exactly meet the
	needs of your target system.  There is nothing special about
	the names given to a set of rules and you may reuse or change
	the names used here. 

	For more information, see the man pages for the define_name_rules(),
	report_name_rules(), change_names(), and report_names() commands. 

******************************************************************************/

/**** 
	EDIF rules: EDIF is case-insensitive and the "&" character is not
	allowed. 
****/
define_name_rules edif -case_insensitive -restrict "&"

/****
	Synopsys' Equation rules: Synopsys' boolean equation format
	allows alphanumerics and a handful of punctuation characters
	in names.  The first character cannot be a "." or ":".
****/
define_name_rules equation -allow "a-z A-Z 0-9 _ \\- . : ,"
define_name_rules equation -first_restrict ".:"

/****
	LSI Logic rules: LSI's netlist format allows alphanumeric
	characters and some punctation.  The first character must be
	alphabetic.  The length of names must be less than 64
	characters.  Names are case insensitive.  A plethora of
	reserved words exist. 

	These rules also apply to the "tdl" output format.
****/
define_name_rules lsi -allow "a-z A-Z 0-9 \\- . _ # &"
define_name_rules lsi -first_restrict "0-9 \\- . _ # &"
define_name_rules lsi -max_length 64
define_name_rules lsi -case_insensitive 
define_name_rules lsi -reserved { "ACPOW", "ACPOWER", "ACTION", 	\
"ANGLE", "ANNOTATIONS",	"BD", "BIDIRECT", "BIDIRECTS", "BLOAT", "BLOCK",\
"BUS", "CELL", "CELSTAT", "CHECK", "CHKSUM", "CLK_LINE", "COMPILE", 	\
"DCPOW", "DCPOWER", "DEF", "DEFINE", "DEL", "DELAYS", "DELETE", "DESC",	\
"DESCRIPTION", "DIRECTORY", "DIR", "DIRECTION", "DUMMY", "END", 	\
"FILEMGR", "FLIP", "FUNCTION", "HM_BIDI", "HM_INPUT", "HM_OUTPUT", "IN",\
"INITIALIZE", "INPUT", "INPUTS", "LEVEL", "LIBRARY", "LIST", "LOAD", 	\
"MOD", "MODULE", "NAME", "NC", "NET", "NOCONNECT", "OPT", "OPTION", 	\
"OPTIONS", "OUT", "OUTPUT", "OUTPUTS", "PIN", "POWERCELLS", "PRIORITY",	\
"PROBE", "PSECURED", "REGION", "SCALE",	"SECURITY", "SIMSUB", 		\
"STRENGTH", "STR", "TAB", "TABLE", "TDL", "TECHNOLOGY", "TSECURED", 	\
"USE", "VIA", "WIRE", "WIRED" }

/****
	Mentor Graphics rules: Mentor's system is case-insensitive and
	net names must be the same as the port they're connected to. 
****/
define_name_rules mentor -case_insensitive -equal_ports_nets

/****
	Verilog rules: Verilog allows alphanumerics and underscore in
	names.  The first character must be alphabetic.  Nets, ports,
	and cells share the same name space; they cannot have the same
	name.  A slew of reserved words are defined. 
****/
define_name_rules verilog -allow "a-z A-Z 0-9 _"
define_name_rules verilog -first_restrict "_ 0-9"
define_name_rules verilog -collapse_name_space
define_name_rules verilog -reserved { "always", "and", "assign",	\
"begin", "buf", "bufif0", "bufif1", "case", "design", "default", 	\
"defparam", "disable", "else", "end", "endcase", "endfunction",		\
"endmodule", "endtask", "event", "for", "force", "forever", "fork", 	\
"function", "highz0", "highz1", "if", "initial", "inout", "input",	\
"integer", "join", "large", "medium", "module",	"nand", "negedge",	\
"nor", "not", "notif0", "notif1", "or", "output", "parameter", 		\
"posedge", "pull0", "pull1", "reg", "release", "repeat", "scalared",	\
"small", "specify", "strong0", "strong1", "supply0", "supply1", "task",	\
"time", "tri", "tri0", "tri1", "trinand", "trior", "trireg", 		\
"vectored", "wait", "wand", "weak0", "weak1", "while", "wire", "wor", 	\
"xor", "xnor" }

/****
	VHDL rules: VHDL is case-insensitive.  Nets, ports, and cells
	share the same name space; they cannot have the same name. 
	Only alpha-numerics and underscore are allowed characters.
	The first character must be an alpha, and the last character
	cannot be an underscore.  A slew of reserved words are defined.
****/
define_name_rules vhdl -case_insensitive -collapse_name_space
define_name_rules vhdl -allowed "A-Z a-z 0-9 _"
define_name_rules vhdl -first_restrict "_ 0-9"
define_name_rules vhdl -last_restrict "_"
define_name_rules vhdl -reserved { "abs", "access", "after", "alias",	\
"all", "and", "architecture", "array", "assert", "attribute", "begin", 	\
"block", "body", "buffer", "bus", "case", "component", "configuration", \
"constant", "disconnect", "downto", "else", "elsif", "end", "entity",	\
"exit", "file", "for", "function", "generate", "generic", "guarded", 	\
"if", "in", "inout", "is", "label", "library", "linkage", "loop", 	\
"map", "mod", "nand", "new", "next", "nor", "not", "null", "of", "on", 	\
"open", "or", "others", "out", "package", "port", "procedure",		\
"process", "range", "record", "register", "rem", "report", "return",	\
"select", "severity", "signal", "subtype", "then", "to", "transport",	\
"type", "units", "until", "use", "variable", "wait", "when", "while",	\
"with", "xor" }