proc2.vhd

design compile synthesis user guide

entity BUS_ARBITRATOR is 
            port(  REQA,REQB,TIMEUP: in BOOLEAN;
              CLK: in BIT;
              reset : BOOLEAN;
              ACKA, ACKB, TIMESTART: out BIT );
            
end;


architecture BEHAVIOR of BUS_ARBITRATOR is
	type STATE_TYPE is ( Grant_A,Grant_B, Wait_A, Wait_B,Timeout_A1,Timeout_B1);
	attribute ENUM_ENCODING: STRING;
	attribute ENUM_ENCODING of STATE_TYPE: type is
	"001 010 011 110 111 101" ;
	signal present_state, next_state: STATE_TYPE;
--  set the state vector attribute
attribute STATE_VECTOR : STRING;
 attribute STATE_VECTOR of BEHAVIOR:
			architecture is "present_state";
begin

 COMBIN: process (REQA, REQB, TIMEUP,  reset, present_State)
	begin

	-- Initialize to the default values 
	next_state<= present_state;
	ACKA <= '0';
	ACKB <= '0';
	TIMESTART <= '0';
	
	if ( reset ) then
	    next_state<= Wait_B;

	else 
	    case ( present_state ) is 

             
	   when  Wait_A => -- Round-robin priority detection 
	            if ( REQB ) then
	                next_state<= Grant_B; ACKB <= '1'; TIMESTART <= '1';

	            elsif ( REQA ) then
                        next_State <= Grant_A; ACKA <= '1'; TIMESTART <= '1';
                    end if;

            when Wait_B => -- Round-robin priority detection 
                    if ( REQA ) then
                        next_State <= Grant_A; ACKA <= '1'; TIMESTART <= '1';

                    elsif ( REQB ) then
                        next_State <= Grant_B; ACKB <= '1'; TIMESTART <= '1';
                    end if;

            when Grant_A =>
	            -- Voluntary processor release of bus 
                    if ( not REQA ) then
                        next_State <= Wait_A;

	            -- Processor timeout -- timeout signal is asserted and 
                    -- some other processor REQuests access to bus         
                    elsif ( TIMEUP and REQB ) then
                        next_State <= Timeout_A1;

	            -- Let processor maintain access to bus 
	            else 
                        ACKA <= '1'; TIMESTART <= '1';
		  end if;
            when Grant_B =>
	            -- Voluntary processor release of bus 
                    if ( not REQB ) then
                        next_State <= Wait_B;

	            -- Processor timeout -- timeout signal is asserted and 
                    -- some other processor REQuests access to bus         
                    elsif ( TIMEUP and REQA ) then
                        next_State <= Timeout_B1;

	            -- Let processor maintain access to bus 
	            else
                        ACKB <= '1'; TIMESTART <= '1';

                   end if;
	    -- Add delay to avoid bus contention after timeout 
	    when Timeout_A1 =>
                    next_State <= Wait_A;

	    -- Add delay to avoid bus contention after timeout 
	    when Timeout_B1 =>
                    next_State <= Wait_B;

            end case;
        end if;
        end process;


SYNCH: process
	begin
		wait until CLK'event and CLK = '1';
   present_State <= next_State;
end process;

end BEHAVIOR;