proc3.v

design compile synthesis user guide

module BUS_ARBITRATOR1( REQA, REQB, TIMEUP, CLK, reset,
                       ACKA, ACKB, TIMESTART , in1,in2,out1 );

input REQA, REQB, TIMEUP, CLK, reset;
output ACKA, ACKB, TIMESTART;
input in1,in2;
output out1;

/* Define states and encodings */
parameter [2:0] // synopsys enum code
          Grant_A=3'b001, Wait_A=3'b011, Timeout_A1=3'b111,
          Grant_B=3'b010, Wait_B=3'b110, Timeout_B1=3'b101;

reg [2:0] /* synopsys enum code */ present_State;

//synopsys state_vector present_State

reg [2:0] next_State;
reg ACKA, ACKB, TIMESTART;

assign out1 = in1 || in2;

 always @ (REQA or REQB or TIMEUP  or reset or present_State)
	begin

	/* Initialize to the default values */
	next_State = present_State;
	{ACKA,ACKB,TIMESTART} = 3'b000;
	
	if ( reset ) begin
	    next_State = Wait_B;
	end

	else begin
	    case ( present_State ) //synopsys parallel_case

             
	    Wait_A: /* Round-robin priority detection */
	            if ( REQB ) begin
	                next_State = Grant_B; ACKB = 1; TIMESTART = 1;
	            end
	            else if ( REQA ) begin
                        next_State = Grant_A; ACKA = 1; TIMESTART = 1;
	            end

            Wait_B: /* Round-robin priority detection */
                    if ( REQA ) begin
                        next_State = Grant_A; ACKA = 1; TIMESTART = 1;
	            end
                    else if ( REQB ) begin
                        next_State = Grant_B; ACKB = 1; TIMESTART = 1;
                    end


            Grant_A:
	            /* Voluntary processor release of bus */
                    if ( !REQA ) 
                        next_State = Wait_A;

	            /* Processor timeout -- timeout signal is asserted and */
                    /* some other processor REQuests access to bus         */
                    else if ( TIMEUP && REQB )
                        next_State = Timeout_A1;

	            /* Let processor maintain access to bus */
	            else begin
                        ACKA = 1; TIMESTART = 1;
	            end

            Grant_B:
	            /* Voluntary processor release of bus */
                    if ( !REQB ) 
                        next_State = Wait_B;

	            /* Processor timeout -- timeout signal is asserted and */
                    /* some other processor REQuests access to bus         */
                    else if ( TIMEUP && REQA )
                        next_State = Timeout_B1;

	            /* Let processor maintain access to bus */
	            else begin
                        ACKB = 1; TIMESTART = 1;
	            end

	    /* Add delay to avoid bus contention after timeout */
	    Timeout_A1:
                    next_State = Wait_A;

	    /* Add delay to avoid bus contention after timeout */
	    Timeout_B1:
                    next_State = Wait_B;

            endcase
        end

	end



  always @(posedge CLK)
   present_State = next_State;

endmodule