drink-st.scr

design compile synthesis user guide

/************************************************************************/
/*		Soft Drink Machine - State Machine Version		*/
/************************************************************************/
/*  									*/
/* This example represents a vending control unit for a soft drink 	*/
/* vending machine.  The circuit reads signals from a coin input unit, 	*/
/* and sends outputs to a change dispensing unit and a drink dispensing	*/
/* unit.  This example design assumes that there is only one kind of 	*/
/* soft drink dispensed.  This is a clocked design, with CLK being the 	*/
/* input clock.  The price of the drink is 35 cents.  Input signals 	*/
/* from the coin input unit are nickel_in (nickel deposited), dime_in 	*/
/* (dime deposited),  and quarter_in (quarter deposited).  Output 	*/
/* signals to the change dispensing unit are nickel_out (nickel change)	*/
/* and dime_out (dime change).  The output signal to the drink 		*/
/* dispensing unit is dispense (dispense drink).  This description 	*/
/* for this design uses a state machine description style. The state  	*/
/* machine can be reset synchronously and is reset if RESET is 1.       */
/*  									*/
/* The VHDL code implementing this example is contained in file 	*/
/* drink-st.vhd 							*/
/*  									*/
/************************************************************************/

/************************************************************************/
/*  									*/
/* To try this example, the following commands would be run:		*/
/* First, set up the path to the libraries. To use a different 		*/
/* technology library, these variables may be changed. 			*/
/*  									*/
/************************************************************************/

search_path = { ., synopsys_root + /libraries/syn}
target_library = {class.db}
symbol_library = {class.sdb}
link_path = {class.db}

/************************************************************************/
/*  									*/
/* The read command is used to read in the VHDL source file.	 	*/
/*  									*/
/*	The read command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

read -format vhdl drink-st.vhd

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/*  									*/
/* The second step is to set up the process environment. This includes 	*/
/* defining the wire load model and the operating conditions. 		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/
set_wire_load "10x10"
set_operating_conditions WCCOM

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/*  									*/
/* Next, set up the conditions at the boundry of the design. This 	*/
/* includes defining the drive level on the input signals, the load on 	*/
/* the outputs, and the arrival times of the input signals.		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_arrival .1 RESET
set_drive 1 all_inputs()
set_load 4 all_outputs()

/************************************************************************/
/*                                                                      */
/* Now, the constraints would be specified. In this example, the goal   */
/* is to create the smallest design. This is specified as shown below.  */
/*  									*/
/*	This command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

max_area 0 

/************************************************************************/
/*  									*/
/* Next, the following command will compile this design			*/
/*									*/
/*	Chapter 5 of the Design Compiler Reference manual describes	*/
/*	the compile command and the different options available.	*/
/*  									*/
/************************************************************************/

compile

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/*  									*/
/* 	The design is now compiled. To view the schematic, bring up 	*/
/* the design analyzer and view the schematic.				*/
/*  									*/
/*  									*/
/*	The report command may be used to find the size and speed of 	*/
/* the design. Selecting the 'Report' button from the Main menu will 	*/
/* display the report types available. The Design Compiler Reference 	*/
/* Manual describes all the available reports. From the dc_shell 	*/
/* command line, a report is generated as shown below.			*/
/*  									*/
/* dc_shell> report -area						*/
/* dc_shell> report -timing						*/
/*  									*/
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