drink-st.vhd

design compile synthesis user guide

entity DRINK_ST is
  port(NICKEL_IN, DIME_IN, QUARTER_IN, RESET: BOOLEAN;
       CLK: BIT;
       NICKEL_OUT, DIME_OUT, DISPENSE: out BOOLEAN);
end;

architecture BEHAVIOR of DRINK_ST is
  type STATE_TYPE is (IDLE, FIVE, TEN, FIFTEEN,
                      TWENTY, TWENTY_FIVE, THIRTY,
                      OWE_DIME);
  signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;
begin

  process(CURRENT_STATE, RESET, NICKEL_IN, DIME_IN, QUARTER_IN)
  begin
    -- Default assignments
    NEXT_STATE <= CURRENT_STATE;
    NICKEL_OUT <= FALSE;
    DIME_OUT <= FALSE;
    DISPENSE <= FALSE;


      -- State transitions and output logic
      case CURRENT_STATE is
        when IDLE =>
          if(NICKEL_IN) then
            NEXT_STATE <= FIVE;
          elsif(DIME_IN) then
            NEXT_STATE <= TEN;
          elsif(QUARTER_IN) then
            NEXT_STATE <= TWENTY_FIVE;
          end if;

        when FIVE =>
          if(NICKEL_IN) then
            NEXT_STATE <= TEN;
          elsif(DIME_IN) then
            NEXT_STATE <= FIFTEEN;
          elsif(QUARTER_IN) then
            NEXT_STATE <= THIRTY;
          end if;

        when TEN =>
          if(NICKEL_IN) then
            NEXT_STATE <= FIFTEEN;
          elsif(DIME_IN) then
            NEXT_STATE <= TWENTY;
          elsif(QUARTER_IN) then
            NEXT_STATE <= IDLE;
            DISPENSE <= TRUE;
          end if;

        when FIFTEEN =>
          if(NICKEL_IN) then
            NEXT_STATE <= TWENTY;
          elsif(DIME_IN) then
            NEXT_STATE <= TWENTY_FIVE;
          elsif(QUARTER_IN) then
            NEXT_STATE <= IDLE;
            DISPENSE <= TRUE;
            NICKEL_OUT <= TRUE;
          end if;

        when TWENTY =>
          if(NICKEL_IN) then
            NEXT_STATE <= TWENTY_FIVE;
          elsif(DIME_IN) then
            NEXT_STATE <= THIRTY;
          elsif(QUARTER_IN) then
            NEXT_STATE <= IDLE;
            DISPENSE <= TRUE;
            DIME_OUT <= TRUE;
          end if;

        when TWENTY_FIVE =>
          if(NICKEL_IN) then
            NEXT_STATE <= THIRTY;
          elsif(DIME_IN) then
            NEXT_STATE <= IDLE;
            DISPENSE <= TRUE;
          elsif(QUARTER_IN) then
            NEXT_STATE <= IDLE;
            DISPENSE <= TRUE;
            DIME_OUT <= TRUE;
            NICKEL_OUT <= TRUE;
          end if;

        when THIRTY =>
          if(NICKEL_IN) then
            NEXT_STATE <= IDLE;
            DISPENSE <= TRUE;
          elsif(DIME_IN) then
            NEXT_STATE <= IDLE;
            DISPENSE <= TRUE;
            NICKEL_OUT <= TRUE;
          elsif(QUARTER_IN) then
            NEXT_STATE <= OWE_DIME;
            DISPENSE <= TRUE;
            DIME_OUT <= TRUE;
          end if;

        when OWE_DIME =>
          NEXT_STATE <= IDLE;
          DIME_OUT <= TRUE;

      end case;
  end process;

 
  -- Synchronize state value with clock.
  -- This causes it to be stored in flip flops
  -- The synchronous reset is impled by emebedding it within
  -- the if clk'event and clk'1.
  process(CLK, RESET)
  begin
    if CLK'event and CLK = '1' then
      if reset then
        CURRENT_STATE <= IDLE;
      else
        CURRENT_STATE <= NEXT_STATE;
      end if;
    end if;
  end process;

end BEHAVIOR;