addsub.vhd

design compile synthesis user guide

library work;
use work.synopsys.all;
use work.attributes.all;

entity addsub is
port	(arg1, arg2 : in signed(6 downto 1);
	 add : in boolean;
	 result : out signed(6 downto 1));
end ;

architecture BV of addsub is
begin
  adsb : process(arg1,arg2,add)
  constant r0 : resource := 0;
  attribute map_to_module of r0 : constant is "DW01_addsub";
  attribute implementation of r0 : constant is "rpl";
  attribute ops of r0 : constant is "a1 a2";  
  begin
    if add then
      result <= arg1 + arg2; -- pragma label a1
    else
      result <= arg1 - arg2; -- pragma label a2
    end if;
  end process;
end BV;