addsub.scr

design compile synthesis user guide

/************************************************************************/
/*	Adder-Subtractor Implementation via Synthetic Libraries		*/
/************************************************************************/
/*									*/
/*   This example will illustrate the use of resource sharing and       */
/* synthetic libraries. There are many ways to implement operators in	*/
/* VHDL. One way is to explicitly define the structure (add-sub.vhd).	*/
/* Another more quick and efficient method to do so is by using 	*/
/* components in the synthetic library. 				*/
/* 									*/
/*   This example addsub.vhd consists of a module that has three inputs,*/
/* two 6 bit data, 1 control and 1 6 bit output. The module will add	*/
/* the two inputs and output the result if control is 1 and output the	*/
/* subtraction of the two if the control is 0. 				*/
/* 									*/
/*   There are many ways that this code can be implmented in. For	*/
/* example, there can be 1 adder and 1 subtractor, an adder/subtractor	*/
/* and each can have their own implementation (ripple, carry look ahead)*/
/* Design complier gives the user the ability to direct the synthesis	*/
/* process by letting dc infer the sharing to be performed and the	*/
/* implementations to be used by inferring them from the constraints	*/
/* given OR via explicit directives in the VHDL code that guide where 	*/
/* and how sharing is to be performed and with which component.		*/
/* 									*/
/*    This example shows how manual directives are given in the VHDL	*/
/* code to direct the design compiler. The directives in the VHDL	*/
/* tell design compiler that the two operations labelled a1 and a2	*/
/* are to be mapped to a combined DW02_addsub component and whose	*/
/* implementation is a ripple type. The manual directive feature is	*/
/* usefull when users know exactly what they want.			*/
/* 									*/
/*  									*/
/* The VHDL code implementing the call to the adder-subtractor with	*/
/* the manual directives is contained in a file addsub.vhd.		*/
/*  									*/
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/************************************************************************/
/*  									*/
/* To try this example, the following commands would be run:		*/
/* First, set up the path to the libraries. To use a different 		*/
/* technology library, these variables may be changed. 			*/
/*									*/
/************************************************************************/

search_path = { ., synopsys_root + /libraries/syn, synopsys_root +\
/packages/synopsys_old/src}
target_library = {class.db}
symbol_library = {class.sdb}
link_path = {class.db}

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/*  									*/
/*      The read command now recognises the library and use clauses     */
/*      thus we have to only read in the design file. The HDL-Compiler  */
/*      will pick up the previously analyzed packages from the library  */
/*	defined in the previous step					*/
/*	The read command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/
read -format vhdl synopsys.vhd
read -format vhdl attributes.vhd
read -format vhdl {addsub.vhd}

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/*  									*/
/* The second step is to set up the process environment. This includes 	*/
/* defining the wire load model and the operating conditions. 		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_wire_load "10x10"
set_operating_conditions WCCOM

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/*  									*/
/* Next, set up the conditions at the boundry of the design. This 	*/
/* includes defining the drive level on the input signals, the load on 	*/
/* the outputs, and the arrival times of the input signals.		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_drive 1 all_inputs()
set_load 4 all_outputs()

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/*  									*/
/* Now, the constraints would be specified. In this example, the goal 	*/
/* is to create the smallest design. This is specified as shown below. 	*/
/*  									*/
/*	This command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

max_area 0

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/*  									*/
/* Next, the following command will compile this design			*/
/*									*/
/*	Chapter 5 of the Design Compiler Reference manual describes	*/
/*	the compile command and the different options available.	*/
/*  									*/
/************************************************************************/

compile

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/*  									*/
/* 	The design is now compiled. To view the schematic, click on 	*/
/* the 'view' button in the Design Compiler Main Menu, or execute	*/
/* the following commands from the dc_shell command line. 		*/
/* The view command does not exist in 3.0, to view schematics please    */
/* bring up the design analyzer						*/
/*  									*/
/* dc_shell> gen -sort							*/
/*  									*/
/*	The report command may be used to find the size and speed of 	*/
/* the design. Selecting the 'Report' button from the Main menu will 	*/
/* display the report types available. The Design Compiler Reference 	*/
/* Manual describes all the available reports. From the dc_shell 	*/
/* command line, a report is generated as shown below.			*/
/*  									*/
/* dc_shell> report -area						*/
/* dc_shell> report -timing						*/
/* The user can also find out what resources are used in the design	*/
/* through the report menu. This is done be selecting the resource 	*/
/* option under the attribute report section of the report menu. This	*/
/* is usefull if the user has not placed any directives in the code,	*/
/* and wishes to find out what/how operators are bieng shared.		*/
/*									*/
/* dc_shell>report_resources						*/
/*  									*/
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