s2p-seq.scr

design compile synthesis user guide

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/*		Serial-to-Parallel Converter - Shifting Bits		*/
/************************************************************************/
/*  									*/
/* This example shows the design of a serial-to-parallel converter.  It */
/* reads a serial, bit-stream input and produces an 8-bit output.       */
/* The design reads the following inputs:                               */
/* SERIAL_IN       Serial input data                                    */
/* RESET        When '1', will cause the converter to reset.  All       */
/*              outputs are set to zero, and the converter is made      */
/*              ready to read the next serial word.                     */
/* CLOCK        The value of the RESET and SERIAL_IN is read on the     */
/*              positive transition of this clock.  Outputs of the     	*/
/*              converter are also only valid on positive transitions. 	*/
/* The design produces the following outputs:                           */
/* PARALLEL_OUT Eight-bit value read from the SERIAL_IN port.        	*/
/* READ_ENABLE  When this output is '1' on the positive transition of	*/
/*              CLOCK, the data on PARALLEL_OUT can be read.            */
/* PARITY_ERROR When this output is '1' on the positive transition of	*/
/*              CLOCK, a parity error was detected on the SERIAL_IN     */
/*              port.  Once a parity error has been detected, the       */
/*              converter halts until restarted by the RESET port.      */
/*                                                                      */
/*  									*/
/* This examples describes another implementation of the last example's	*/
/*  serial-to-parallel converter.  This design performs the same 	*/
/* function as the previous one, but uses a different algorithm to do 	*/
/* the conversion.  In the previous implementation, a counter was used 	*/
/* to indicate which bit of the output was set when a new serial bit 	*/
/* was read.  In this implementation, the serial bits are shifted into 	*/
/* place.  Before the conversion takes place, a '1 ' is placed in the 	*/
/* least-significant bit position.  When that '1' is shifted out of 	*/
/* the most significant position (position 0) the signal NEXT_HIGH_BIT 	*/
/* is set to '1' and the conversion is complete				*/
/*  									*/
/* Notice that the synthesized schematic for the shifter implementation	*/
/* is much simpler than the first.  This is because the "shifter" 	*/
/* algorithm is inherently easier to implement.  With the "count" 	*/
/* algorithm, each of the flip-flops holding the PARALLEL_OUT bits 	*/
/* needed logic which decoded the value stored in the BIT_POSITION 	*/
/* flip-flops to see when to route in the value of SERIAL_IN.  		*/
/* Additionally, the BIT_POSITION flip-flops needed an incrementer to 	*/
/* compute their next value.						*/
/*  									*/
/* In contrast, the "shifter" algorithm requires no incrementer, and 	*/
/* no flip flops to hold BIT_POSITION.  Additionally, the logic in 	*/
/* front of most PARALLEL_OUT bits needs only to read the value of 	*/
/* the previous flip-flop, or '0', depending on whether bits are 	*/
/* currently being read.  In the "shifter" algorithm, the SERIAL_IN 	*/
/* port needs only to be connected to the least significant bit 	*/
/* (number 7) of the PARALLEL_OUT flip flops.  These two 		*/
/* implementations illustrate the importance of designing efficient 	*/
/* algorithms.  Both will work properly, but the better algorithm 	*/
/* produced a faster, more area-efficient design.			*/
/*  									*/
/* The VHDL code implementing this example is contained in file		*/ 
/* s2p-seq.vhd & types-pack.vhd						*/
/*  									*/
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/************************************************************************/
/*  									*/
/* To try this example, the following commands would be run:		*/
/* First, set up the path to the libraries. To use a different 		*/
/* technology library, these variables may be changed. 			*/
/*  									*/
/************************************************************************/

search_path = { ., synopsys_root + /libraries/syn}
target_library = {class.db}
symbol_library = {class.sdb}
link_path = {class.db}

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/*  									*/
/* The read command is used to read in the VHDL source file. In this 	*/
/* example, the local package and the source file will be read in.  	*/
/*  									*/
/*	The read command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

read -format vhdl { types-pack.vhd s2p-seq.vhd }

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/*  									*/
/* The second step is to set up the process environment. This includes 	*/
/* defining the wire load model and the operating conditions. 		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_wire_load "10x10"
set_operating_conditions WCCOM

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/*  									*/
/* Next, set up the conditions at the boundry of the design. This 	*/
/* includes defining the drive level on the input signals, the load on 	*/
/* the outputs, and the arrival times of the input signals.		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_drive 1 all_inputs()
set_load 4 all_outputs()

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/*                                                                      */
/* Now, the constraints would be specified. In this example, the goal   */
/* is to create the smallest design. This is specified as shown below.  */
/*  									*/
/*	This command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
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max_area 0

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/*  									*/
/* Next, the following command will compile this design			*/
/*									*/
/*	Chapter 5 of the Design Compiler Reference manual describes	*/
/*	the compile command and the different options available.	*/
/*  									*/
/************************************************************************/

compile 

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/*  									*/
/* 	The design is now compiled. To view the schematic, click on 	*/
/* the 'view' button in the Design Compiler Main Menu, or execute	*/
/* the following commands from the dc_shell command line. 		*/
/*  									*/
/* dc_shell> gen -sort							*/
/* dc_shell> view							*/
/*  									*/
/*	The report command may be used to find the size and speed of 	*/
/* the design. Selecting the 'Report' button from the Main menu will 	*/
/* display the report types available. The Design Compiler Reference 	*/
/* Manual describes all the available reports. From the dc_shell 	*/
/* command line, a report is generated as shown below.			*/
/*  									*/
/* dc_shell> report -area						*/
/* dc_shell> report -timing						*/
/*  									*/
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