cnt-seq.vhd

design compile synthesis user guide

entity COUNT_SEQ_VHDL is
  port(DATA, CLK: in BIT;
       RESET, READ: in BOOLEAN;
       COUNT: buffer INTEGER range 0 to 8;
       IS_LEGAL: out BOOLEAN;
       COUNT_READY: out BOOLEAN);
end;
 
architecture BEHAVIOR of COUNT_SEQ_VHDL is
begin
  process
    variable SEEN_ZERO, SEEN_TRAILING: BOOLEAN;
    variable BITS_SEEN: INTEGER range 0 to 7;
  begin
    wait until CLK'event and CLK = '1';
 
    if(RESET) then
      COUNT_READY <= FALSE;
      IS_LEGAL <= TRUE;
      SEEN_ZERO := FALSE;
      SEEN_TRAILING := FALSE;
      COUNT <= 0;
      BITS_SEEN := 0;
    else
      if (READ) then
        if (SEEN_TRAILING and DATA = '0') then
          IS_LEGAL <= FALSE;
          COUNT <= 0;
          COUNT_READY <= TRUE;
        elsif (SEEN_ZERO and DATA = '1') then
          SEEN_TRAILING := TRUE;
        elsif (DATA = '0') then
          SEEN_ZERO := TRUE;
          COUNT <= COUNT + 1;
        end if;
 
 
        if (BITS_SEEN = 7) then
          COUNT_READY <= TRUE;
        else
          BITS_SEEN :=  BITS_SEEN + 1;
        end if;

      end if;    -- if (READ)
    end if;    -- if (RESET)
  end process;
end BEHAVIOR;