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design compile synthesis user guide

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/*		 	Carry-lookahead Adder				*/
/************************************************************************/
/* This examples demonstrates the use of concurrent procedure calls to 	*/
/* build a 32-bit carry-lookahead adder.  The adder is built by 	*/
/* partitioning the 32-bit input into eight slices of four bits each.	*/
/* Each of the eight slices computes propagate and generate values 	*/
/* using the PG procedure.						*/
/*  									*/
/* "Propagate" (output P from PG) is '1' for a bit position if that 	*/
/* position will propagate a carry from the next lower position to the 	*/
/* next higher position.  "Generate" (output G) is '1' for a bit 	*/
/* position if that position will generate a carry to the next higher 	*/
/* position, regardless of the carry-in from the next lower position.	*/
/*  									*/
/* The carry-lookahead logic reads the carry-in, propagate, and 	*/
/* generate information computed from the inputs.  It computes the 	*/
/* carry value for each bit position.  This makes the addition 		*/
/* operation just an XOR of the inputs and the carry values.		*/
/*  									*/
/* The carry values are computed by a three-level tree of four-bit 	*/
/* carry- lookahead blocks.  The first level of the tree computes the 	*/
/* 32 carry values and the eight group propagate and generate values.	*/
/* The first-level group propagate and generate values tell if that 	*/
/* group of bits will propagate and generate carry values from the 	*/
/* next lower group to the next higher.  The first-level lookahead 	*/
/* blocks read the group carry computed at the second level.		*/
/*  									*/
/* The second-level lookahead blocks read the group propagate and 	*/
/* generate information from the four first-level blocks, then 		*/
/* compute their own group propagate and generate information.  They 	*/
/* also read group carry information computed at the third level to 	*/
/* compute the carries for each of the third-level blocks.		*/
/*  									*/
/* The third-level block reads the propagate and generate information 	*/
/* of the second level to compute a propagate and generate value for 	*/
/* the entire adder.  It also reads the external carry to compute 	*/
/* each second-level carry.  The carry-out for the adder is '1' if 	*/
/* the third-level generate is '1', or if the third-level propagate 	*/
/* is '1' and the external carry is '1'.				*/
/*  									*/
/* The third-level carry-lookahead block is capable of processing 	*/
/* four second- level blocks.  Since there are only two, the high-	*/
/* order two bits of the computed carry are ignored, the high-order 	*/
/* two bits of the generate input to the third-level are set to zero,	*/
/*  and the propagate high-order bits are set to one.  This causes 	*/
/* the unused portion to propagate carries but not to generate them.	*/
/*  									*/
/* The VHDL implementation of this design is done with four procedures:	*/
/* CLA     A four-bit carry-lookahead block.				*/
/* PG      Computes first-level propagate and generate information.	*/
/* SUM     Computes the sum by "xor"ing the inputs with the carry 	*/
/* 	   values computed by CLA.					*/
/* BITSLICE    Collects together the first-level CLA blocks, the 	*/
/* 	   PG computations and the SUM.  This procedure performs all 	*/
/* 	   the work for a four-bit value except for the second- and 	*/
/* third-level lookaheads.						*/
/*  									*/
/* In this implementation, procedures were used to perform the 		*/
/* computation of the design.  The procedures could have been written 	*/
/* as separate entities and then used by component instantiation.  	*/
/* This would cause a hierarchical design to be produced, since the 	*/
/* VHDL Compiler does not collapse the hierarchy of entities, while 	*/
/* it does collapse the procedure call hierarchy into one design.	*/
/*  									*/
/* Note that the keyword signal is included before some of the 		*/
/* interface parameter declarations.  This is required for out formal 	*/
/* parameters when the actual parameters must be signals.		*/
/*  									*/
/* The output parameter C from the CLA procedure was not declared 	*/
/* as a signal.  This makes it illegal to use it in a concurrent 	*/
/* procedure call (since only signals may be used in such calls).  To 	*/
/* overcome this, sub-processes were used, declaring a temporary 	*/
/* variable TEMP.  TEMP receives the value of the C parameter and 	*/
/* then assigns it to the appropriate signal.  This a generally 	*/
/* useful technique.							*/
/*  									*/
/* The VHDL code implementing this examples is contained in file 	*/
/* cla.vhd and local-pack.vhd 						*/
/*  									*/
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/************************************************************************/
/*  									*/
/* To try this example, the following commands would be run:		*/
/* First, set up the path to the libraries. To use a different 		*/
/* technology library, these variables may be changed. 			*/
/*  									*/
/************************************************************************/

search_path = { ., synopsys_root + /libraries/syn}
target_library = {class.db}
symbol_library = {class.sdb}
link_path = {class.db}

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/*  									*/
/* The read command is used to read in the VHDL source file. In this 	*/
/* example, the local package and the cla source file will be read in.  */
/*  									*/
/*	The read command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

read -format vhdl { local-pack.vhd cla.vhd }

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/*  									*/
/* The second step is to set up the process environment. This includes 	*/
/* defining the wire load model and the operating conditions. 		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_wire_load "10x10"
set_operating_conditions WCCOM

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/*  									*/
/* Next, set up the conditions at the boundry of the design. This 	*/
/* includes defining the drive level on the input signals, the load on 	*/
/* the outputs, and the arrival times of the input signals.		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
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set_drive 1 all_inputs()
set_load 4 all_outputs()

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/*  									*/
/* Now, the constraints would be specified. In this example, the design	*/
/* must generate the output in 40 ns. This is specified as shown below.	*/
/*  									*/
/*	This command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
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max_delay 40.0 S[31]

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/*  									*/
/* Next, the following command will compile this design			*/
/*									*/
/*	Chapter 5 of the Design Compiler Reference manual describes	*/
/*	the compile command and the different options available.	*/
/*  									*/
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compile 

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/*  									*/
/* 	The design is now compiled. To view the schematic, click on 	*/
/* the 'view' button in the Design Compiler Main Menu, or execute	*/
/* the following commands from the dc_shell command line. 		*/
/*  									*/
/* dc_shell> gen -sort							*/
/* dc_shell> view							*/
/*  									*/
/*	The report command may be used to find the size and speed of 	*/
/* the design. Selecting the 'Report' button from the Main menu will 	*/
/* display the report types available. The Design Compiler Reference 	*/
/* Manual describes all the available reports. From the dc_shell 	*/
/* command line, a report is generated as shown below.			*/
/*  									*/
/* dc_shell> report -area						*/
/* dc_shell> report -timing						*/
/*  									*/
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