command.log

design compile synthesis user guide

symbol_name_layer.visible = "true"
symbol_source_suffix = {"slib"}
synopsys_program_name = "dc_shell"
synopsys_root = "/remote/release/v2.2a"
synthetic_library = {"standard.sldb"}
target_library = {"simple.db"}
tdlout_upcase = "true"
technology_library_suffix = {"db"}
technology_source_suffix = {"lib"}
template_layer.blue = 45875
template_layer.green = 45875
template_layer.line_width = 3
template_layer.red = 0
template_layer.scalable_lines = "false"
template_layer.visible = "true"
template_naming_style = "%s_%p"
template_parameter_style = "%s%d"
template_separator_style = "_"
template_text_layer.blue = 65535
template_text_layer.green = 65535
template_text_layer.red = 65535
template_text_layer.visible = "true"
test_clock_port_naming_style = "test_c%s"
test_scan_clock_a_port_naming_style = "test_sca%s"
test_scan_clock_b_port_naming_style = "test_scb%s"
test_scan_clock_port_naming_style = "test_sc%s"
test_scan_enable_inverted_port_naming_style = "test_sei%s"
test_scan_enable_port_naming_style = "test_se%s"
test_scan_in_port_naming_style = "test_si%s%s"
test_scan_out_port_naming_style = "test_so%s%s"
text_change_select_region_mode = "basic"
text_editor_command = "xterm -fn 8x13 -e vi %s &"
text_print_command = "lpr -Plw"
text_threshold = 6
text_unselect_on_button_press = "true"
uniquify_naming_style = "%s_%d"
use_port_name_for_oscs = "true"
user_home_path = "/remote/osi15/randyj"
variable_layer.visible = "false"
verbose_messages = "true"
verilogout_equation = "false"
verilogout_no_tri = "false"
verilogout_single_bit = "false"
verilogout_time_scale = 1.000000
verilogout_top_instance_name = "u1"
vhdllib_glitch_handle = "true"
vhdllib_timing_mesg = "true"
vhdllib_timing_xgen = "false"
vhdlout_bit_type = "BIT"
vhdlout_bit_vector_type = "BIT_VECTOR"
vhdlout_conversion_functions = {}
vhdlout_dont_write_types = "false"
vhdlout_equations = "false"
vhdlout_isolate_type_conversions = "FALSE"
vhdlout_local_attributes = "true"
vhdlout_one_name = "'1'"
vhdlout_preserve_hierarchical_types = "FALSE"
vhdlout_single_bit = "true"
vhdlout_target_simulator = ""
vhdlout_three_state_name = "'Z'"
vhdlout_three_state_res_func = ""
vhdlout_time_scale = 1.000000
vhdlout_unknown_name = "'X'"
vhdlout_upcase = "false"
vhdlout_use_packages = {}
vhdlout_wired_and_res_func = ""
vhdlout_wired_or_res_func = ""
vhdlout_write_attributes = "false"
vhdlout_write_components = "TRUE"
vhdlout_write_constraints = "false"
vhdlout_zero_name = "'0'"
view_arch_types = {"apollo", "decmips", "hp300", "hp700", "mips", "necmips", "rs6000", "sgimips", "sonymips", "sun3", "sparc"}
view_background = "black"
view_banner_font = "9x15"
view_busy_during_selection = "false"
view_command_log_file = "command_log.out"
view_dialogs_modal = "true"
view_disable_cursor_warping = "true"
view_disable_error_windows = "false"
view_error_window_count = 3
view_execute_script_suffix = {".script", ".scr", ".dcs", ".dcv", ".dc", ".con"}
view_extend_thick_lines = "true"
view_icon_font = "8x13"
view_icon_path = "/remote/release/v2.2a/sparc/syn/auxx/icons"
view_ignore_source_file_dates = "true"
view_log_file = "view_log.script"
view_num_lines_to_auto_scroll = 0
view_pixels_per_route_grid = 0
view_read_file_suffix = {"db", "sdb", "edif", "eqn", "fnc", "lsi", "mif", "NET", "pla", "st", "tdl", "v", "vhd", "vhdl"}
view_set_cursor_area = 8
view_set_selecting_color = ""
view_use_small_cursor = ""
view_use_x_routines = "true"
view_win_height = 500
view_win_width = 600
view_write_file_suffix = {"db", "sdb", "do", "edif", "eqn", "fnc", "lsi", "NET", "neted", "pla", "st", "tdl", "v", "vhd", "vhdl"}
working_path = "/remote/osi15/randyj/examples/vhdl/cla"
write_name_nets_same_as_ports = "false"
x11_set_cursor_background = ""
x11_set_cursor_foreground = ""
x11_set_cursor_number = "-1"


/* Initial dc_shell Aliases */


alias cde          	"current_design ="
alias free         	"remove_design"
alias fsm_minimize 	"minimize_fsm"
alias fsm_reduce   	"reduce_fsm"
alias gen          	"create_schematic"
alias group_bus    	"create_bus"
alias groupvar     	"group_variable"
alias gv           	"gen -sort ;view"
alias lint         	"check_design"
alias ls           	"sh ls -AC"
alias map          	"compile -no_flatten -no_s -map 1"
alias q            	"quit"
alias re           	"read -f equation"
alias report_area  	"report -area"
alias report_cell  	"report -cell"
alias report_clock 	"report_clocks"
alias report_clock_constraint 	"report -clock_constraint"
alias report_clock_tree 	"report -clock_tree"
alias report_compile_options 	"report -compile_options"
alias report_constraint 	"report_constraints"
alias report_design 	"report -design"
alias report_fsm   	"report -fsm"
alias report_hierarchy 	"report -hierarchy"
alias report_internal_loads 	"report -internal_loads"
alias report_net   	"report -net"
alias report_port  	"report -port"
alias report_power 	"report -power"
alias report_reference 	"report -reference"
alias report_register 	"report -register"
alias report_synthetic 	"report -cell"
alias report_xref  	"report -xref"
alias rlsi         	"read -f lsi"
alias rpla         	"read -f pla"
alias rv           	"read -f verilog"
alias rvhdl        	"read -f vhdl"
alias set_internal_arrival 	"set_arrival"
alias set_internal_load 	"set_load"
alias sge          	"edifout_no_array = true ; edifout_merge_libraries = true ; edifout_external = false ; edifout_power_and_ground_representation = cell ; "
alias ungroup_bus  	"remove_bus"
alias ver          	"list product_version"
alias verify       	"compare_design"
alias view_cursor_number 	"x11_set_cursor_number"
alias we           	"write -f equation"
alias wlsi         	"write -f lsi"
alias wpla         	"write -f pla"
alias wrvhdl       	"write -f vhdl"
alias wv           	"write -f verilog"


/* dc_shell Command Log */ 


/************************************************************************/ 
/*		 	Carry-lookahead Adder				*/ 
/************************************************************************/ 
/* This examples demonstrates the use of concurrent procedure calls to 	*/ 
/* build a 32-bit carry-lookahead adder.  The adder is built by 	*/ 
/* partitioning the 32-bit input into eight slices of four bits each.	*/ 
/* Each of the eight slices computes propagate and generate values 	*/ 
/* using the PG procedure.						*/ 
/*  									*/ 
/* "Propagate" (output P from PG) is '1' for a bit position if that 	*/ 
/* position will propagate a carry from the next lower position to the 	*/ 
/* next higher position.  "Generate" (output G) is '1' for a bit 	*/ 
/* position if that position will generate a carry to the next higher 	*/ 
/* position, regardless of the carry-in from the next lower position.	*/ 
/*  									*/ 
/* The carry-lookahead logic reads the carry-in, propagate, and 	*/ 
/* generate information computed from the inputs.  It computes the 	*/ 
/* carry value for each bit position.  This makes the addition 		*/ 
/* operation just an XOR of the inputs and the carry values.		*/ 
/*  									*/ 
/* The carry values are computed by a three-level tree of four-bit 	*/ 
/* carry- lookahead blocks.  The first level of the tree computes the 	*/ 
/* 32 carry values and the eight group propagate and generate values.	*/ 
/* The first-level group propagate and generate values tell if that 	*/ 
/* group of bits will propagate and generate carry values from the 	*/ 
/* next lower group to the next higher.  The first-level lookahead 	*/ 
/* blocks read the group carry computed at the second level.		*/ 
/*  									*/ 
/* The second-level lookahead blocks read the group propagate and 	*/ 
/* generate information from the four first-level blocks, then 		*/ 
/* compute their own group propagate and generate information.  They 	*/ 
/* also read group carry information computed at the third level to 	*/ 
/* compute the carries for each of the third-level blocks.		*/ 
/*  									*/ 
/* The third-level block reads the propagate and generate information 	*/ 
/* of the second level to compute a propagate and generate value for 	*/ 
/* the entire adder.  It also reads the external carry to compute 	*/ 
/* each second-level carry.  The carry-out for the adder is '1' if 	*/ 
/* the third-level generate is '1', or if the third-level propagate 	*/ 
/* is '1' and the external carry is '1'.				*/ 
/*  									*/ 
/* The third-level carry-lookahead block is capable of processing 	*/ 
/* four second- level blocks.  Since there are only two, the high-	*/ 
/* order two bits of the computed carry are ignored, the high-order 	*/ 
/* two bits of the generate input to the third-level are set to zero,	*/ 
/*  and the propagate high-order bits are set to one.  This causes 	*/ 
/* the unused portion to propagate carries but not to generate them.	*/ 
/*  									*/ 
/* The VHDL implementation of this design is done with four procedures:	*/ 
/* CLA     A four-bit carry-lookahead block.				*/ 
/* PG      Computes first-level propagate and generate information.	*/ 
/* SUM     Computes the sum by "xor"ing the inputs with the carry 	*/ 
/* 	   values computed by CLA.					*/ 
/* BITSLICE    Collects together the first-level CLA blocks, the 	*/ 
/* 	   PG computations and the SUM.  This procedure performs all 	*/ 
/* 	   the work for a four-bit value except for the second- and 	*/ 
/* third-level lookaheads.						*/ 
/*  									*/ 
/* In this implementation, procedures were used to perform the 		*/ 
/* computation of the design.  The procedures could have been written 	*/ 
/* as separate entities and then used by component instantiation.  	*/ 
/* This would cause a hierarchical design to be produced, since the 	*/ 
/* VHDL Compiler does not collapse the hierarchy of entities, while 	*/ 
/* it does collapse the procedure call hierarchy into one design.	*/ 
/*  									*/ 
/* Note that the keyword signal is included before some of the 		*/ 
/* interface parameter declarations.  This is required for out formal 	*/ 
/* parameters when the actual parameters must be signals.		*/ 
/*  									*/ 
/* The output parameter C from the CLA procedure was not declared 	*/ 
/* as a signal.  This makes it illegal to use it in a concurrent 	*/ 
/* procedure call (since only signals may be used in such calls).  To 	*/ 
/* overcome this, sub-processes were used, declaring a temporary 	*/ 
/* variable TEMP.  TEMP receives the value of the C parameter and 	*/ 
/* then assigns it to the appropriate signal.  This a generally 	*/ 
/* useful technique.							*/ 
/*  									*/ 
/* The VHDL code implementing this examples is contained in file 	*/ 
/* cla.vhd and local-pack.vhd 						*/ 
/*  									*/ 
/************************************************************************/ 
/************************************************************************/ 
/*  									*/ 
/* To try this example, the following commands would be run:		*/ 
/* First, set up the path to the libraries. To use a different 		*/ 
/* technology library, these variables may be changed. 			*/ 
/*  									*/ 
/************************************************************************/ 
search_path = { ., synopsys_root + /libraries/syn} 
target_library = {class.db} 
symbol_library = {class.sdb} 
link_path = {class.db} 
/************************************************************************/ 
/*  									*/ 
/* The read command is used to read in the VHDL source file. In this 	*/ 
/* example, the local package and the cla source file will be read in.  */ 
/*  									*/ 
/*	The read command is described in the Design Compiler Command	*/ 
/* 	Reference Manual.						*/ 
/*  									*/ 
/************************************************************************/ 
read -format vhdl { local-pack.vhd cla.vhd } 
/************************************************************************/ 
/*  									*/ 
/* The second step is to set up the process environment. This includes 	*/ 
/* defining the wire load model and the operating conditions. 		*/ 
/*  									*/ 
/*	These commands are described in the Design Compiler Command	*/ 
/* 	Reference Manual.						*/ 
/*  									*/ 
/************************************************************************/ 
set_wire_load "10x10" 
set_operating_conditions WCCOM 
/************************************************************************/ 
/*  									*/ 
/* Next, set up the conditions at the boundry of the design. This 	*/ 
/* includes defining the drive level on the input signals, the load on 	*/ 
/* the outputs, and the arrival times of the input signals.		*/ 
/*  									*/ 
/*	These commands are described in the Design Compiler Command	*/ 
/* 	Reference Manual.						*/ 
/*  									*/ 
/************************************************************************/ 
set_drive 1 all_inputs() 
set_load 4 all_outputs() 
/************************************************************************/ 
/*  									*/ 
/* Now, the constraints would be specified. In this example, the design	*/ 
/* must generate the output in 40 ns. This is specified as shown below.	*/ 
/*  									*/ 
/*	This command is described in the Design Compiler Command	*/ 
/* 	Reference Manual.						*/ 
/*  									*/ 
/************************************************************************/ 
max_delay 40.0 S[31] 
/************************************************************************/ 
/*  									*/ 
/* Next, the following command will compile this design			*/ 
/*									*/ 
/*	Chapter 5 of the Design Compiler Reference manual describes	*/ 
/*	the compile command and the different options available.	*/ 
/*  									*/ 
/************************************************************************/ 
compile  
/************************************************************************/ 
/*  									*/ 
/* 	The design is now compiled. To view the schematic, click on 	*/ 
/* the 'view' button in the Design Compiler Main Menu, or execute	*/ 
/* the following commands from the dc_shell command line. 		*/ 
/*  									*/ 
/* dc_shell> gen -sort							*/ 
/* dc_shell> view							*/ 
/*  									*/ 
/*	The report command may be used to find the size and speed of 	*/ 
/* the design. Selecting the 'Report' button from the Main menu will 	*/ 
/* display the report types available. The Design Compiler Reference 	*/ 
/* Manual describes all the available reports. From the dc_shell 	*/ 
/* command line, a report is generated as shown below.			*/ 
/*  									*/ 
/* dc_shell> report -area						*/ 
/* dc_shell> report -timing						*/ 
/*  									*/ 
/************************************************************************/ 
quit