cla.vhd

design compile synthesis user guide

use WORK.LOCAL.ALL;

---------------------------------
-- A 32-bit carry-lookahead adder
---------------------------------

entity ADDER is
  port(A, B: in BIT_VECTOR(31 downto 0);
       CIN: in BIT;
       S: out BIT_VECTOR(31 downto 0);
       COUT: out BIT);
end ADDER;

architecture BEHAVIOR of ADDER is

  signal GG,GP,GC: BIT_VECTOR(7 downto 0);
    -- First-level generate, propagate, carry
  signal GGG, GGP, GGC: BIT_VECTOR(3 downto 0);
    -- Second-level gen, prop, carry
  signal GGGG, GGGP: BIT;
    -- Third-level gen, prop

begin
  -- Compute Sum and 1st-level Generate and Propagate
  -- Use input data and the 1st-level Carries computed
  -- later.
  BITSLICE(A( 3 downto  0),B( 3 downto  0),GC(0),
           S( 3 downto  0),GP(0), GG(0));
  BITSLICE(A( 7 downto  4),B( 7 downto  4),GC(1),
           S( 7 downto  4),GP(1), GG(1));
  BITSLICE(A(11 downto  8),B(11 downto  8),GC(2),
           S(11 downto  8),GP(2), GG(2));
  BITSLICE(A(15 downto 12),B(15 downto 12),GC(3),
           S(15 downto 12),GP(3), GG(3));
  BITSLICE(A(19 downto 16),B(19 downto 16),GC(4),
           S(19 downto 16),GP(4), GG(4));
  BITSLICE(A(23 downto 20),B(23 downto 20),GC(5),
           S(23 downto 20),GP(5), GG(5));
  BITSLICE(A(27 downto 24),B(27 downto 24),GC(6),
           S(27 downto 24),GP(6), GG(6));
  BITSLICE(A(31 downto 28),B(31 downto 28),GC(7),
           S(31 downto 28),GP(7), GG(7));

  -- Compute first-level Carries and second-level
  -- generate and propagate.
  -- Use first-level Generate, Propagate, and
  -- second-level carry.
  process(GP, GG, GGC)
    variable TEMP: BIT_VECTOR(3 downto 0);
  begin
    CLA(GP(3 downto 0), GG(3 downto 0), GGC(0), TEMP,
        GGP(0), GGG(0));
    GC(3 downto 0) <= TEMP;
  end process;

process(GP, GG, GGC)
    variable TEMP: BIT_VECTOR(3 downto 0);
  begin
    CLA(GP(7 downto 4), GG(7 downto 4), GGC(1), TEMP,
        GGP(1), GGG(1));
    GC(7 downto 4) <= TEMP;
  end process;

  -- Compute second-level Carry and third-level
  --   Generate and Propagate
  -- Use second-level Generate, Propagate and Carry-in
  --   (CIN)
  process(GGP, GGG, CIN)
    variable TEMP: BIT_VECTOR(3 downto 0);
  begin
    CLA(GGP, GGG, CIN, TEMP, GGGP, GGGG);
    GGC <= TEMP;
  end process;

  -- Assign unused bits of second-level Generate and
  --   Propagate
  GGP(3 downto 2) <= "11";
  GGG(3 downto 2) <= "00";

  -- Compute Carry-out (COUT)
  -- Use third-level Generate and Propagate and
  --   Carry-in (CIN).
  COUT <= GGGG or (GGGP and CIN);
end BEHAVIOR;