mealy.scr

design compile synthesis user guide

/************************************************************************/
/*				Mealy Machine 				*/
/************************************************************************/
/* This example shows a simple Mealy finite-state machine, summarized 	*/
/* in Appendix C.  Of the Compiler Reference Manual. It has one 	*/
/* input (X), four internal states (S0 to S3), and one output (Z): 	*/
/*  									*/
/* 	Present	 Next	Output						*/
/*  	state	 State	 (Z)						*/
/*	----------------------------					*/
/* 		X=0 X=1							*/
/*    	S0	S0  S2    0						*/
/*    	S1	S0  S2    1						*/
/*    	S2	S2  S3    1						*/
/*    	S3 	S3  S1    0						*/
/*  									*/
/* The VHDL code implementing this finite-state machine is contained in	*/
/* file Mealy.vhd 							*/
/* The machine is described using two processes.  One process defines 	*/
/* the synchronous elements of the design (state registers). The other 	*/
/* process defines the combinational part of the design (state 		*/
/* assignment case statement).  See the discussion under wait Statement */
/* in Chapter 6 for more details on using two processes.		*/
/*  									*/
/************************************************************************/

/************************************************************************/
/*  									*/
/* To try this example, the following commands would be run:		*/
/* First, set up the path to the libraries. To use a different 		*/
/* technology library, these variables may be changed. 			*/
/*  									*/
/************************************************************************/

search_path = { ., synopsys_root + /libraries/syn}
target_library = {class.db}
symbol_library = {class.sdb}
link_path = {class.db}

/************************************************************************/
/*  									*/
/* The read command is used to read in the VHDL source file.	 	*/
/*  									*/
/*	The read command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

read -format vhdl mealy.vhd

/************************************************************************/
/*  									*/
/* The second step is to set up the process environment. This includes 	*/
/* defining the wire load model and the operating conditions. 		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_wire_load "10x10"
set_operating_conditions WCCOM

/************************************************************************/
/*  									*/
/* Next, set up the conditions at the boundary of the design. This 	*/
/* includes defining the drive level on the input signals, the load on 	*/
/* the outputs, and the arrival times of the input signals.		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_arrival .1 X 
set_drive 1 all_inputs()
set_load 4 all_outputs()

/************************************************************************/
/*  									*/
/* Now, the constraints would be specified. In this example, the clock	*/
/* period is 8 ns. This is specified as shown below. The clock defined  */
/* below has 50% duty cycle. Users can also define their own duty cycle */
/*									*/
/*	This command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

create_clock -period 8 -waveform {0 4} {CLOCK}

/************************************************************************/
/* The following three commented commands are used to get reports on    */
/* FSM's								*/
/*									*/
/*									*/
/*This is to allow the extract command to work on the described FSM	*/
/*									*/
/* dc_shell>replace_synthetic						*/
/*									*/
/* The extract command will extract the FSM features such as default    */
/* state, what kind of reset etc and report_fsm will display them       */
/* dc_shell> extract							*/
/*									*/
/* The folowing command will tell you the default state assignment code	*/
/* and the names of the state registers					*/
/* dc_shell> report -fsm 						*/
/*									*/
/* An user can get a less detailed report by typing in report -fsm      */
/* before typing in replace_synthetic and extract.			*/
/************************************************************************/


/* The user can modify the default state encoding with the following 	*/
/* command.								*/
set_fsm_encoding { "S0=2#00" "S1=2#10" "S2=2#01" "S3=2#11" }		

/* To try and reduce the FSM use the following command			*/
set_fsm_minimize true


/************************************************************************/
/*  									*/
/* Next, the following command will compile this design			*/
/*									*/
/*	Chapter 5 of the Design Compiler Reference manual describes	*/
/*	the compile command and the different options available.	*/
/*  									*/
/************************************************************************/


compile

/************************************************************************/
/*  									*/
/* 	The design is now compiled. To view the schematic, click on 	*/
/* the 'view' button in the Design Compiler Main Menu, or execute	*/
/* the following commands from the dc_shell command line. 		*/
/*  									*/
/* dc_shell> gen -sort							*/
/* dc_shell> view							*/
/*  									*/
/*	The report command may be used to find the size and speed of 	*/
/* the design. Selecting the 'Report' button from the Main menu will 	*/
/* display the report types available. The Design Compiler Reference 	*/
/* Manual describes all the available reports. From the dc_shell 	*/
/* command line, a report is generated as shown below.			*/
/*  									*/
/* dc_shell> report -area						*/
/* dc_shell> report -timing						*/
/*  									*/
/************************************************************************/