mealy.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 63 行

entity MEALY is            -- Mealy machine
  port(X, CLOCK, RESET: in BIT;
       Z: out BIT);
end;

architecture BEHAVIOR of MEALY is
  type STATE_TYPE is (S0, S1, S2, S3);
  signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;
  attribute STATE_VECTOR : STRING;
  attribute STATE_VECTOR of BEHAVIOR : architecture is "CURRENT_STATE";

begin

  -- Process to hold combinational logic.
  COMBIN: process(CURRENT_STATE, X)
  begin
    case CURRENT_STATE is
      when S0 =>
        if X = '0' then
          Z <= '0';
          NEXT_STATE <= S0;
        else
          Z <= '1';
          NEXT_STATE <= S2;
        end if;
      when S1 =>
        if X = '0' then
          Z <= '0';
          NEXT_STATE <= S0;
        else
          Z <= '0';
          NEXT_STATE <= S2;
        end if;
      when S2 =>
        if X = '0' then
          Z <= '1';
          NEXT_STATE <= S2;
        else
          Z <= '0';
          NEXT_STATE <= S3;
        end if;
       when S3 =>
        if X = '0' then
          Z <= '0';
          NEXT_STATE <= S3;
        else
          Z <= '1';
          NEXT_STATE <= S1;
        end if;
    end case;
  end process;
 
  -- Process to hold synchronous elements (flip-flops)
  SYNCH: process(CLOCK, RESET)
  begin
    if (RESET = '0' ) then
      CURRENT_STATE <= S0;
    elsif (CLOCK'EVENT AND CLOCK = '1') then
      CURRENT_STATE <= NEXT_STATE;
    end if;
  end process;
end BEHAVIOR;