smart-gen.scr

design compile synthesis user guide

/************************************************************************/
/*			Smart Waveform Generator 			*/
/************************************************************************/
/*  									*/
/* This example is an extension of the previous example's waveform 	*/
/* generator.  This "smart" waveform generator is capable of holding 	*/
/* the waveform, at any time step, for several clock cycles. Figure 	*/
/* C-4 in appendix C of the VHDL Compiler reference manual shows a 	*/
/* waveform, similar to the waveform of the previous example, where 	*/
/* several of the time steps are held for multiple clock cycles: it 	*/
/* is similar to the waveform generator of the previous example, but	*/
/* with two additions.  A new ROM, D_ROM, has been added to hold the 	*/
/* length of each time step.  A value of 1 specifies that the 		*/
/* corresponding time step should be 1 clock cycle long; a value of 80 	*/
/* specifies the the time step should be 80 clock cycles long. The 	*/
/* second addition to the previous waveform generator is a delay 	*/
/* counter that counts out the clock cycles between time steps. Note 	*/
/* that in the architecture of this example, a selected signal 		*/
/* assignment is used to determine the value of the NEXT_STEP counter.	*/
/*  									*/
/* The VHDL code implementing this example is smart-gen.vhd		*/
/*  									*/
/************************************************************************/

/************************************************************************/
/*  									*/
/* To try this example, the following commands would be run:		*/
/* First, set up the path to the libraries. To use a different 		*/
/* technology library, these variables may be changed. 			*/
/*  									*/
/************************************************************************/

search_path = { ., synopsys_root + /libraries/syn}
target_library = {class.db}
symbol_library = {class.sdb}
link_path = {class.db}

/************************************************************************/
/*  									*/
/* The read command is used to read in the VHDL source file.	 	*/
/*  									*/
/*	The read command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

read -format vhdl smart-gen.vhd

/************************************************************************/
/*  									*/
/* The second step is to set up the process environment. This includes 	*/
/* defining the wire load model and the operating conditions. 		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_wire_load "10x10"
set_operating_conditions WCCOM

/************************************************************************/
/*  									*/
/* Next, set up the conditions at the boundry of the design. This 	*/
/* includes defining the drive level on the input signals, the load on 	*/
/* the outputs, and the arrival times of the input signals.		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_arrival .1 RESET 
set_drive 1 all_inputs()
set_load 4 all_outputs()

/************************************************************************/
/*  									*/
/* Now, the constraints are specified. In this example,we want the 	*/
/* smallest circuit possible. This is specified as shown below.		*/
/*  									*/
/*	This command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

max_area 0

/************************************************************************/
/*  									*/
/* Next, the following command will compile this design			*/
/*									*/
/*	Chapter 5 of the Design Compiler Reference manual describes	*/
/*	the compile command and the different options available.	*/
/*  									*/
/************************************************************************/

compile

/************************************************************************/
/*  									*/
/* 	The design is now compiled. To view the schematic, click on 	*/
/* the 'view' button in the Design Compiler Main Menu, or execute	*/
/* the following commands from the dc_shell command line. 		*/
/*  									*/
/* dc_shell> gen -sort							*/
/* dc_shell> view							*/
/*  									*/
/*	The report command may be used to find the size and speed of 	*/
/* the design. Selecting the 'Report' button from the Main menu will 	*/
/* display the report types available. The Design Compiler Reference 	*/
/* Manual describes all the available reports. From the dc_shell 	*/
/* command line, a report is generated as shown below.			*/
/*  									*/
/* dc_shell> report -area						*/
/* dc_shell> report -timing						*/
/*  									*/
/************************************************************************/