moore.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 61 行

entity MOORE is                -- Moore machine
  port(X, CLOCK, RESET: in BIT;
       Z: out BIT);
end;

architecture BEHAVIOR of MOORE is
  type STATE_TYPE is (S0, S1, S2, S3);
  signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;
-- The next two lines are aynopsys state machine attributes
-- see chapter 4, section on state vector attributes
  attribute STATE_VECTOR : STRING;
  attribute STATE_VECTOR of BEHAVIOR : architecture is "CURRENT_STATE";
begin

  -- Process to hold combinational logic
  COMBIN: process(CURRENT_STATE, X)
  begin
    case CURRENT_STATE is
      when S0 =>
        Z <= '0';
        if X = '0' then
          NEXT_STATE <= S0;
        else
          NEXT_STATE <= S2;
        end if;
      when S1 =>
        Z <= '1';
        if X = '0' then
          NEXT_STATE <= S0;
        else
          NEXT_STATE <= S2;
        end if;
      when S2 =>
        Z <= '1';
        if X = '0' then
          NEXT_STATE <= S2;
        else
          NEXT_STATE <= S3;
        end if;
      when S3 =>
        Z <= '0';
        if X = '0' then
          NEXT_STATE <= S3;
        else
          NEXT_STATE <= S1;
        end if;
    end case; 
end process;

  -- Process to hold synchronous elements (flip-flops)
  SYNCH: process(CLOCK,RESET)
  begin
    if (RESET = '0') then  -- define an asynchronous reset
      CURRENT_STATE <= S0; -- define the reset state
    elsif (CLOCK'EVENT and CLOCK = '1') then
      CURRENT_STATE <= NEXT_STATE;
    end if;
  end process;
end BEHAVIOR;