pla.scr

design compile synthesis user guide

/************************************************************************/
/*			Programmable Logic Array (PLA)			*/
/************************************************************************/
/*  									*/
/* This example shows a way to build PLAs in VHDL.  The PLA function 	*/
/* uses an input lookup vector as an index into a constant PLA table, 	*/
/* then returns the output vector specified by the PLA.			*/
/*  									*/
/* The PLA table is an array of PLA_ROWs, where each row is an array 	*/
/* of PLA_ELEMENTs.  Each element is either a 1, 0, minus, or space 	*/
/* ('1', '0', '- ', or ' ').  The table is split into an input plane 	*/
/* and an output plane.  The input  plane is specified by 0s, 1s, 	*/
/* and minuses.  The output plane is specified by 0s and 1s.  The two 	*/
/* planes' values are separated by a space.				*/
/*  									*/
/* The PLA function works as follows.  The output vector is first 	*/
/* initialized to be all '0's.  When the input vector matches an 	*/
/* input plane in a row of the PLA table, the '1's in the output 	*/
/* plane are assigned to the corresponding bits in the output vector.  	*/
/* A match is determined as follows:					*/
/*  									*/
/*       If there is a '0' or '1' in the input plane, the input 	*/
/* vector must have the same value in the same position.		*/
/*  									*/
/*       If there is a '-' in the input plane, it matches any input 	*/
/* vector value at that position.					*/
/*  									*/
/* The generic PLA table types and the PLA function are defined in a 	*/
/* package named LOCAL.  An entity PLA_VHDL which uses LOCAL needs 	*/
/* only to specify its PLA table as a constant, and then call the 	*/
/* PLA function.							*/
/*  									*/
/* Note that the PLA function does not explicitly depend on the size 	*/
/* of the PLA.  To change the size of the PLA, you would need only to 	*/
/* change the initialization of the TABLE constant and the 		*/
/* initialization of the constants INPUT_COUNT, OUTPUT_COUNT and 	*/
/* ROW_COUNT.  Notice in listing that these constants were 		*/
/* initialized to a PLA which is equivalent to the ROM shown 		*/
/* previously.  Accordingly, the synthesized schematic is the same 	*/
/* as that of the ROM.							*/
/*  									*/
/* This example was included mainly to illustrate the capabilities 	*/
/* of VHDL.  It would be much more efficient to define the PLA 		*/
/* directly, using the PLA input format; see the Design Compiler 	*/
/* Reference Manual for more information.				*/
/*  									*/
/* The VHDL code implementing this example is contained in file		*/ 
/* s2p-count.vhd & types-pack.vhd					*/
/*  									*/
/************************************************************************/

/************************************************************************/
/*  									*/
/* To try this example, the following commands would be run:		*/
/* First, set up the path to the libraries. To use a different 		*/
/* technology library, these variables may be changed. 			*/
/*  									*/
/************************************************************************/

search_path = { ., synopsys_root + /libraries/syn}
target_library = {class.db}
symbol_library = {class.sdb}
link_path = {class.db}

/************************************************************************/
/*  									*/
/* The read command is used to read in the VHDL source file. In this 	*/
/* example, the local package and the pla source file will be read in.  */
/*  									*/
/*	The read command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

read -format vhdl { local-pack.vhd pla.vhd }

/************************************************************************/
/*  									*/
/* The second step is to set up the process environment. This includes 	*/
/* defining the wire load model and the operating conditions. 		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_wire_load "10x10"
set_operating_conditions WCCOM

/************************************************************************/
/*  									*/
/* Next, set up the conditions at the boundry of the design. This 	*/
/* includes defining the drive level on the input signals, the load on 	*/
/* the outputs, and the arrival times of the input signals.		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_drive 1 all_inputs()
set_load 4 all_outputs()

/************************************************************************/
/*  									*/
/* Now, the constraints would be specified. In this example, the goal	*/
/* is to create the smallest design. This is specified as shown below. 	*/
/*  									*/
/*	This command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

max_area 0

/************************************************************************/
/*  									*/
/* Next, the following command will compile this design			*/
/*									*/
/*	Chapter 5 of the Design Compiler Reference manual describes	*/
/*	the compile command and the different options available.	*/
/*  									*/
/************************************************************************/

compile

/************************************************************************/
/*  									*/
/* 	The design is now compiled. To view the schematic, click on 	*/
/* the 'view' button in the Design Compiler Main Menu, or execute	*/
/* the following commands from the dc_shell command line. 		*/
/*  									*/
/* dc_shell> gen -sort							*/
/* dc_shell> view							*/
/*  									*/
/*	The report command may be used to find the size and speed of 	*/
/* the design. Selecting the 'Report' button from the Main menu will 	*/
/* display the report types available. The Design Compiler Reference 	*/
/* Manual describes all the available reports. From the dc_shell 	*/
/* command line, a report is generated as shown below.			*/
/*  									*/
/* dc_shell> report -area						*/
/* dc_shell> report -timing						*/
/*  									*/
/************************************************************************/