local-pack.vhd

design compile synthesis user guide

package LOCAL is
  constant INPUT_COUNT: INTEGER := 3;
  constant OUTPUT_COUNT: INTEGER := 5;
  constant ROW_COUNT: INTEGER := 6;
  constant ROW_SIZE: INTEGER := INPUT_COUNT +
                                OUTPUT_COUNT + 1;
  type PLA_ELEMENT is ('1', '0', '-', ' ');
  type PLA_VECTOR is
      array (INTEGER range <>) of PLA_ELEMENT;
  subtype PLA_ROW is
      PLA_VECTOR(ROW_SIZE - 1 downto 0);
  subtype PLA_OUTPUT is
      PLA_VECTOR(OUTPUT_COUNT - 1 downto 0);
  type PLA_TABLE is
      array(ROW_COUNT - 1 downto 0) of PLA_ROW;

  function PLA(IN_VECTOR: BIT_VECTOR;
               TABLE: PLA_TABLE)
      return BIT_VECTOR;
end LOCAL;


package body LOCAL is

  function PLA(IN_VECTOR: BIT_VECTOR;
               TABLE: PLA_TABLE)
      return BIT_VECTOR is
    subtype RESULT_TYPE is
        BIT_VECTOR(OUTPUT_COUNT - 1 downto 0);
    variable RESULT: RESULT_TYPE;
    variable ROW: PLA_ROW;
    variable MATCH: BOOLEAN;
    variable IN_POS: INTEGER;
  begin
    RESULT := RESULT_TYPE'(others => BIT'( '0' ));

    for I in TABLE'range loop
      ROW := TABLE(I);

      MATCH := TRUE;
      IN_POS := IN_VECTOR'left;

      -- Check for match in input plane
      for J in ROW_SIZE - 1 downto OUTPUT_COUNT loop
        if(ROW(J) = PLA_ELEMENT'( '1' )) then
          MATCH := MATCH and
                   (IN_VECTOR(IN_POS) = BIT'( '1' ));
        elsif(ROW(J) = PLA_ELEMENT'( '0' )) then
          MATCH := MATCH and
                   (IN_VECTOR(IN_POS) = BIT'( '0' ));
        else
          null;      -- Must be minus ("don't care")
        end if;
        IN_POS := IN_POS - 1;
      end loop;

      -- Set output plane
      if(MATCH) then
        for J in RESULT'range loop
          if(ROW(J) = PLA_ELEMENT'( '1' )) then
            RESULT(J) := BIT'( '1' );
          end if;
        end loop;
      end if;
    end loop;

    return(RESULT);
  end;
end LOCAL;