s2p-count.scr

design compile synthesis user guide

/************************************************************************/
/*		Serial-to-Parallel Converter - Counting Bits		*/
/************************************************************************/
/* This example shows the design of a serial-to-parallel converter. It  */
/* reads a serial, bit-stream input and produces an 8-bit output.	*/
/* The design reads the following inputs:				*/
/* SERIAL_IN       Serial input data					*/
/* RESET	When '1', will cause the converter to reset.  All 	*/
/* 		outputs are set to zero, and the converter is made 	*/
/* 		ready to read the next serial word.			*/
/* CLOCK   	The value of the RESET and SERIAL_IN is read on the	*/
/*		 positive transition of this clock.  Outputs of the 	*/
/*		 converter are also only valid on positive transitions.	*/
/* The design produces the following outputs:				*/
/* PARALLEL_OUT  Eight-bit value read from the SERIAL_IN port.		*/
/* READ_ENABLE   When this output is '1' on the positive transition of	*/
/*		 CLOCK, the data on PARALLEL_OUT can be read.		*/
/* PARITY_ERROR  When this output is '1' on the positive transition of	*/
/*		 CLOCK, a parity error was detected on the SERIAL_IN	*/
/*		 port.  Once a parity error has been detected, the 	*/
/*		 converter halts until restarted by the RESET port.	*/
/* 									*/
/* When no data is being transmitted to the serial port, it should be 	*/
/* kept at a value of '0'.  Each eight-bit value requires ten clock 	*/
/* cycles to read; on the eleventh clock cycle, the parallel output 	*/
/* value can be read.  In the first cycle, a '1' is placed on the 	*/
/* serial input. This indicates that an eight-bit value follows.  	*/
/* The next eight cycles are used to transmit each bit of the value.	*/
/* The most significant bit is transmitted first.  The tenth and 	*/
/* final cycle is used to transmit the parity of the eight bit value.  	*/
/* It must be '0' if there were an even  number of '1's in the 8-bit 	*/
/* data, and '1' otherwise. If the converter detects a parity error, 	*/
/* then the PARITY_ERROR output is set to '1' and the circuit waits 	*/
/* until it is reset.							*/
/* 									*/
/* On the eleventh cycle, the READ_ENABLE output is set to '1', and the	*/
/* 8-bit value may be read from the PARALLEL_OUT port. If the SERIAL_IN */
/* port has a '1' on the eleventh cycle, then another eight-bit value is*/
/* read immediately; otherwise, the converter waits until SERIAL_IN goes*/
/* to '1'.								*/
/* 									*/
/* The converter is implemented as a four-state finite state machine 	*/
/* with synchronous reset.  When a reset is detected, the WAIT_FOR_START*/
/* start is entered.  The following describes each state:		*/
/* 									*/
/* WAIT_FOR_START							*/
/*	 Stay in this state until a '1' is detected on the serial input.*/
/*	 When a '1' is detected, clear the parallel_out registers	*/
/*	 and go to the READ_BITS state.					*/
/* 									*/
/* READ_BITS								*/
/*	 If the value of the current_bit_position counter is 8, then	*/
/*	 all eight bits have been read.  Check the computed parity	*/
/*	 with the transmitted parity; if correct, go to the ALLOW_READ	*/
/*	 state, otherwise go to the PARITY_ERROR state.			*/
/*	 If all eight bits have not yet been read, then the set the	*/
/*	 appropriate bit in the parallel_out buffer to the		*/
/*	 serial_in value, compute the parity of the bits read so far,	*/
/*	 and increment the current_bit_position.			*/
/* 									*/
/* ALLOW_READ      							*/
/*	 This is the state where the outside world reads the		*/
/*	 parallel_out value.  When that value is read, the design	*/
/*	 returns to the WAIT_FOR_START state.				*/
/* 									*/
/* PARITY_ERROR_DETECTED						*/
/*	 When in this state, the parity_error output is set to '1',	*/
/*	 and nothing else is done.					*/
/* This design has four values stored in registers:			*/
/* 									*/
/* CURRENT_STATE							*/
/*	 Remembers the state as of the last clock edge.			*/
/* 									*/
/* CURRENT_BIT_POSITION							*/
/*	 Remembers how many bits have been read so far.			*/
/* 									*/
/* CURRENT_PARITY							*/
/*	 Keeps a running "xor" of the bits read.			*/
/* 									*/
/* CURRENT_PARALLEL_OUT							*/
/*	 Stores each parallel bit as it is found.			*/
/* 									*/
/* The design is divided into two processes:  the combinational 	*/
/* NEXT_ST, containing the combinational logic, and the sequential 	*/
/* SYNCH, which is clocked.						*/
/* 									*/
/* NEXT_ST performs all the computations and state assignments.		*/
/* 									*/
/* The NEXT_ST process starts by first assigning default values to 	*/
/* all of the signals it drives.  This guarantees that all signals 	*/
/* are driven under all conditions.  Next, the RESET input is processed.*/
/* If RESET is not active, then a case statement determines the current */
/* state and its computations.  State transitions are performed by 	*/
/* assigning the next desired state's value to the NEXT_STATE signal.	*/
/* 									*/
/* The serial-to-parallel conversion itself is performed by these two 	*/
/* statements in the NEXT_ST process:					*/
/* 									*/
/*	NEXT_PARALLEL_OUT(CURRENT_BIT_POSITION) <= SERIAL_IN;		*/
/*	NEXT_BIT_POSITION <= CURRENT_BIT_POSITION + 1;			*/
/* 									*/
/* The first statement assigns the current serial input bit to a 	*/
/* particular bit of the parallel output.  The second statement 	*/
/* increments the next bit position to be assigned.			*/
/* 									*/
/* SYNCH registers and updates the stored values described above.  	*/
/* Each registered signal has parts, CURRENT_... and NEXT_...  The 	*/
/* NEXT_...  signals hold values computed by the NEXT_ST process.  	*/
/* The CURRENT_...  signals hold the values driven by the SYNCH 	*/
/* process.  The CURRENT_...  signals hold the values of the NEXT_... 	*/
/* signals as of the last clock edge.					*/
/*  									*/
/* The VHDL code implementing this example is contained in file		*/ 
/* s2p-count.vhd & types-pack.vhd					*/
/*  									*/
/************************************************************************/

/************************************************************************/
/*  									*/
/* To try this example, the following commands would be run:		*/
/* First, set up the path to the libraries. To use a different 		*/
/* technology library, these variables may be changed. 			*/
/*  									*/
/************************************************************************/

search_path = { ., synopsys_root + /libraries/syn}
target_library = {class.db}
symbol_library = {class.sdb}
link_path = {class.db}

/************************************************************************/
/*  									*/
/* The read command is used to read in the VHDL source file. In this 	*/
/* example, the local package and the source file will be read in.  	*/
/*  									*/
/*	The read command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

read -format vhdl { types-pack.vhd s2p-count.vhd }

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/*  									*/
/* The second step is to set up the process environment. This includes 	*/
/* defining the wire load model and the operating conditions. 		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_wire_load "10x10"
set_operating_conditions WCCOM

/************************************************************************/
/*  									*/
/* Next, set up the conditions at the boundry of the design. This 	*/
/* includes defining the drive level on the input signals, the load on 	*/
/* the outputs, and the arrival times of the input signals.		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_drive 1 all_inputs()
set_load 4 all_outputs()

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/*                                                                      */
/* Now, the constraints would be specified. In this example, the goal   */
/* is to create the smallest design. This is specified as shown below.  */
/*  									*/
/*	This command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

max_area 0

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/*  									*/
/* Next, the following command will compile this design			*/
/*									*/
/*	Chapter 5 of the Design Compiler Reference manual describes	*/
/*	the compile command and the different options available.	*/
/*  									*/
/************************************************************************/

compile 

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/*  									*/
/* 	The design is now compiled. To view the schematic, click on 	*/
/* the 'view' button in the Design Compiler Main Menu, or execute	*/
/* the following commands from the dc_shell command line. 		*/
/*  									*/
/* dc_shell> gen -sort							*/
/* dc_shell> view							*/
/*  									*/
/*	The report command may be used to find the size and speed of 	*/
/* the design. Selecting the 'Report' button from the Main menu will 	*/
/* display the report types available. The Design Compiler Reference 	*/
/* Manual describes all the available reports. From the dc_shell 	*/
/* command line, a report is generated as shown below.			*/
/*  									*/
/* dc_shell> report -area						*/
/* dc_shell> report -timing						*/
/*  									*/
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