rom.scr

design compile synthesis user guide

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/*			    Read-only Memory				*/
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/* This example shows how a ROM may be specified in VHDL.  The ROM is	*/
/* specified as an array constant, ROM.  Each line of the constant 	*/
/* array's specification defines the contents of one ROM address.  To 	*/
/* read from the ROM, simply index into the array.			*/
/* 									*/
/* The ROM's number of storage locations and bit width may be easily	*/
/* changed.  The subtype ROM_RANGE specifies that the ROM contains	*/
/* storage locations 0 to 7.  The constant ROM_WIDTH specifies that the	*/
/* ROM is 5 bits wide.							*/
/* 									*/
/* Once you have defined a ROM constant, you may index into that	*/
/* constant many times to read many values from the ROM.  If the ROM	*/
/* address is computable (see Computable Operands in Chapter 5), then	*/
/* no logic is built.  The appropriate data value is simply inserted.	*/
/* If the ROM address is not computable then logic is built for each	*/
/* index into the value.  For this not computable then logic is built	*/
/* for each index into the value.  For this reason, you should consider	*/
/* resource sharing when using a ROM (see Resource Sharing in Chapter	*/
/* 9).  In the example, ADDR is not computable, so logic is synthesized	*/
/* to compute the value.						*/
/* 									*/
/* The VHDL Compiler does not actually instantiate a typical 		*/
/* array-logic ROM, such as those available from ASIC vendors. Instead,	*/
/* the ROM is created from random logic gates (AND, OR, NOT, etc.).  	*/
/* This type of	implementation is preferable for small ROMs, or for 	*/
/* ROMs which are very regular. For very large ROMs, you should 	*/
/* probably consider using an array-logic implementation that is 	*/
/* supplied by your ASIC vendor.					*/
/* 									*/
/* The VHDL code implementing this example is contained in ROM.vhd	*/
/*  									*/
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/*  									*/
/* To try this example, the following commands would be run:		*/
/* First, set up the path to the libraries. To use a different 		*/
/* technology library, these variables may be changed. 			*/
/*  									*/
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search_path = { ., synopsys_root + /libraries/syn}
target_library = {class.db}
symbol_library = {class.sdb}
link_path = {class.db}

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/*  									*/
/* The read command is used to read in the VHDL source file.	 	*/
/*  									*/
/*	The read command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
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read -format vhdl ROM.vhd

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/*  									*/
/* The second step is to set up the process environment. This includes 	*/
/* defining the wire load model and the operating conditions. 		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
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set_wire_load "10x10"
set_operating_conditions WCCOM

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/*  									*/
/* Next, set up the conditions at the boundry of the design. This 	*/
/* includes defining the drive level on the input signals, the load on 	*/
/* the outputs, and the arrival times of the input signals.		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
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set_drive 1 all_inputs()
set_load 4 all_outputs()

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/*  									*/
/* Now, the constraints would be specified. In this example, the goal	*/
/* is to create the smallest circuit. This is specified as shown below. */
/*  									*/
/*	This command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
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max_area 0

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/*  									*/
/* Next, the following command will compile this design			*/
/*									*/
/*	Chapter 5 of the Design Compiler Reference manual describes	*/
/*	the compile command and the different options available.	*/
/*  									*/
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compile

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/*  									*/
/* 	The design is now compiled. To view the schematic, click on 	*/
/* the 'view' button in the Design Compiler Main Menu, or execute	*/
/* the following commands from the dc_shell command line. 		*/
/*  									*/
/* dc_shell> gen -sort							*/
/* dc_shell> view							*/
/*  									*/
/*	The report command may be used to find the size and speed of 	*/
/* the design. Selecting the 'Report' button from the Main menu will 	*/
/* display the report types available. The Design Compiler Reference 	*/
/* Manual describes all the available reports. From the dc_shell 	*/
/* command line, a report is generated as shown below.			*/
/*  									*/
/* dc_shell> report -area						*/
/* dc_shell> report -timing						*/
/*  									*/
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