cnt-combin.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 43 行

module count_zeros(in, out, error);
   input  [7:0] in;
   output [3:0] out;
   output error;

   function legal;
   input [7:0] x;
   reg seenZero, seenTrailing;
   integer i;

   begin : _legal_block
      legal = 1; seenZero = 0; seenTrailing = 0;
      for ( i=0; i <= 7; i=i+1 )
         if ( seenTrailing && (x[i] == 0) ) begin
            legal = 0;
            disable _legal_block;
            end
         else if ( seenZero && (x[i] == 1) )
            seenTrailing = 1;
         else if ( x[i] == 0 )
            seenZero = 1;
      end
   endfunction
      
  function [3:0] zeros;
   input [7:0] x;
   reg   [3:0] count;
   integer i;
 
   begin
      count = 0;
      for ( i=0; i <= 7; i=i+1 )
         if ( x[i] == 0 ) count = count + 1;
         zeros = count;
      end
   endfunction
      
   wire is_legal = legal(in);
   assign error = ! is_legal;
   assign out   = is_legal ? zeros(in) : 0;
endmodule