cnt-seq.scr

design compile synthesis user guide

/************************************************************************/
/*			Count Zeros - Sequential			*/
/************************************************************************/
/*  									*/
/* This "count zeros" example is from a design problem where an 8-bit 	*/
/* value is given, and the circuit is to determine two things: first, 	*/
/* that there is exactly one sequence of 0s in the value, and second, 	*/
/* the number of 0s in that sequence (if any). 
/*  									*/
/* A legal value is one that contains only one consecutive series of 	*/
/* zeros.  If more than one series of zeros appears, then the value is 	*/
/* illegal.  A value consisting entirely of ones is defined as a legal 	*/
/* value.  If a value is illegal, then the zero counter is reset (to 	*/
/* zero).  For example, the value 00000000 is legal and has 8 zeros; 	*/
/* value 11000111 is legal and has 3 zeros; value 001111100 is not 	*/
/* legal.								*/
/*  									*/
/* This example shows a sequential (clocked) variant of the "count 	*/
/* zeros" problem. The circuit accepts the 8-bit data value serially, 	*/
/* one bit per clock cycle, using the DATA and CLK inputs.  The other 	*/
/* two inputs are RESET, which resets the circuit, and READ, which 	*/
/* causes the circuit to begin accepting the data bits.			*/
/*  									*/
/* The circuit's three outputs are: is_legal, which is true if the 	*/
/* data was a legal value, data_ready, which is true at the first 	*/
/* illegal bit or when all eight bits have been processed, and zeros, 	*/
/* the number of zeros if is_legal is true.				*/
/*  									*/
/* This example shows a sequential (serial) approach to counting 	*/
/* the zeros; the next example shows a combinational (parallel)		*/
/*  approach.								*/
/*  									*/
/* The Verilog code implementing this example is contained in file 	*/
/* cnt-seq.v								*/
/*  									*/
/************************************************************************/

/************************************************************************/
/*  									*/
/* To try this example, the following commands would be run:		*/
/* First, set up the path to the libraries. To use a different 		*/
/* technology library, these variables may be changed. 			*/
/*  									*/
/************************************************************************/

search_path = { ., synopsys_root + /libraries/syn}
target_library = {class.db}
symbol_library = {class.sdb}
link_path = {class.db}

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/*  									*/
/* The read command is used to read in the Verilog source file.	 	*/
/*  									*/
/*	The read command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

read -format verilog cnt-seq.v

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/*  									*/
/* The second step is to set up the process environment. This includes 	*/
/* defining the wire load model and the operating conditions. 		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_wire_load "10x10"
set_operating_conditions WCCOM

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/*  									*/
/* Next, set up the conditions at the boundry of the design. This 	*/
/* includes defining the drive level on the input signals, the load on 	*/
/* the outputs, and the arrival times of the input signals.		*/
/*  									*/
/*	These commands are described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

set_drive 1 all_inputs()
set_load 4 all_outputs()

/************************************************************************/
/*  									*/
/* Now, the constraints would be specified. In this example, the 	*/
/* design must generate a the count and error signals within 20 ns. 	*/
/* Additionally, the design must not take up more than 175 gates.	*/
/* This is specified as shown below. 					*/
/*  									*/
/*	This command is described in the Design Compiler Command	*/
/* 	Reference Manual.						*/
/*  									*/
/************************************************************************/

max_delay 20.0 all_outputs()
max_area 175

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/*  									*/
/* Next, the following command will compile this design			*/
/*									*/
/*	Chapter 5 of the Design Compiler Reference manual describes	*/
/*	the compile command and the different options available.	*/
/*  									*/
/************************************************************************/

compile 

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/*  									*/
/* 	The design is now compiled. To view the schematic, click on 	*/
/* the 'view' button in the Design Compiler Main Menu, or execute	*/
/* the following commands from the dc_shell command line. 		*/
/*  									*/
/* dc_shell> gen -sort							*/
/* dc_shell> view							*/
/*  									*/
/*	The report command may be used to find the size and speed of 	*/
/* the design. Selecting the 'Report' button from the Main menu will 	*/
/* display the report types available. The Design Compiler Reference 	*/
/* Manual describes all the available reports. From the dc_shell 	*/
/* command line, a report is generated as shown below.			*/
/*  									*/
/* dc_shell> report -area						*/
/* dc_shell> report -timing						*/
/*  									*/
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