cla.v

design compile synthesis user guide

module cla_16(a, b, c_in, sum, c_out, gen_out, prop_out);

input [15:0] a, b;     // numbers to add
input c_in;            // carry in
output [15:0] sum;     // sum
output c_out;          // carry of 16-bit addition
output gen_out;        // generate of 16-bit addition
output prop_out;      // propagate of 16-bit addition

wire [3:0] part_carry; // calculated carry_out of
                       //each 4-bit part
wire [3:0] part_gen;   // generate of each 4-bit part
wire [3:0] part_prop;  // propagate of each 4-bit part
// Make instances to calculate generates and propagates.
// First 4 instances calculate generate and propagate
// for each 4-bit part.  Last instance calculates
// generate and propagate for all 16 bits.

gen_prop gp0( (a[3:0] & b[3:0]), (a[3:0] | b[3:0]),
              part_gen[0], part_prop[0]);

gen_prop gp1( (a[7:4] & b[7:4]), (a[7:4] | b[7:4]),
              part_gen[1], part_prop[1]);

gen_prop gp2( (a[11:8] & b[11:8]), (a[11:8] | b[11:8]),
              part_gen[2], part_prop[2]);

gen_prop gp3( (a[15:12] & b[15:12]), (a[15:12] | b[15:12]),
              part_gen[3], part_prop[3]);

gen_prop gp(part_gen, part_prop, gen_out, prop_out);

// Make instances to calculate carries for each 4-bit part
carry c( part_gen, part_prop, c_in, part_carry );
assign c_out = part_carry[3];

// make 4-bit adders to do additions

assign sum[3:0] = a[3:0] + b[3:0] + c_in;
assign sum[7:4] = a[7:4] + b[7:4] + part_carry[0];
assign sum[11:8] = a[11:8] + b[11:8] + part_carry[1];
assign sum[15:12] = a[15:12] + b[15:12] + part_carry[2];
endmodule

module carry(gens_in, props_in, c_in, carries);
input [3:0] gens_in;  // generate for each of 4 parts
input [3:0] props_in; // propagate for each of 4 parts
input c_in;           // carry in
 
output [3:0] carries;  // carry out for each of 4 parts
 
 
function [3:0] get_carries;
input [3:0] gens_in, props_in;
input c_in;
reg [3:0] carries;
integer i;
 
begin
   for (i = 0; i <= 3; i = i + 1)
      if (i == 0)
         carries[i] = gens_in[i] | props_in[i] & c_in;
      else
         carries[i] = gens_in[i] | props_in[i] &
                                             carries[i-1];
   get_carries = carries;
end
endfunction
 
assign carries = get_carries(gens_in, props_in, c_in);
endmodule
module gen_prop(gens_in, props_in, gen_out, prop_out);
 
input [3:0] gens_in;  // generate for each of 4 parts
input [3:0] props_in; // propagate for each of 4 parts
output gen_out, prop_out;
 
function [1:0] get_gen_and_prop;
input [3:0] gens_in, props_in;
reg prop, gen;
integer i;
 
begin
   for (i = 0; i <= 3; i = i + 1) begin
      if (i == 0) begin
         gen = gens_in[i];
         prop = props_in[i];
      end else begin
         gen = gens_in[i] | props_in[i] & gen;
         prop = props_in[i] & prop;
      end
   end
 
get_gen_and_prop = {gen, prop};
end
endfunction

assign {gen_out, prop_out} = get_gen_and_prop(gens_in, props_in);
endmodule