example.rpt

design compile synthesis user guide

    oD........(0->16)-bit MEM_READ_SEQ_OP_read_cs_rr100x50_state_1 reset_loop/operational_loop/read_write_loop/MEM_READ_cell_ram_mem_read1/seq_cell_5
    oz........(8_16_0)-bit MEM_WRITE_SEQ_OP_write_cs_rr100x50_state_0 reset_loop/operational_loop/read_write_loop/MEM_WRITE_cell_ram_mem_write/seq_cell_7


***************************************************************************
***************************************************************************
               Date      : Fri Dec  3 17:19:04 1999
               Version   : 2000.05-SI1
               Design    : example
***************************************************************************

**************************************
*  Summary report for process main:  *
**************************************
---------------------------------------------------------------------------
     Timing Summary
---------------------------------------------------------------------------
 Clock period 20.00
 Loop timing information:
    main...........................................17 cycles (cycles 0 - 17)
        reset_loop.................................17 cycles (cycles 0 - 17)
            operational_loop.......................16 cycles (cycles 1 - 17)
                start_loop..........................1 cycle  (cycles 1 - 2)
                    (exit) EXIT_L78......................... (cycle 2)
                read_write_loop.....................9 cycles (cycles 6 - 15)
                    (exit) EXIT_L93......................... (cycle 7)
---------------------------------------------------------------------------
     Area Summary
---------------------------------------------------------------------------
 Estimated combinational area    1815
 Estimated sequential area       1320
 TOTAL                           3135

 18 control states
 20 basic transitions
 4 control inputs
 26 control outputs

---------------------------------------------------------------------------
     Resource types
---------------------------------------------------------------------------
	Register Types
========================================
	1-bit register.....................2
	6-bit register.....................1
	8-bit register.....................1
	16-bit register....................4

	Operator Types
========================================
	(6_6->1)-bit DW01_cmp2.............1
	(7_7->8)-bit DW01_add..............1
	(8_8->16)-bit DW02_mult............1
	(8_8_16->16)-bit cs_rr100x50.......1
	(16->16)-bit DW01_inc..............1
	(16_16->16)-bit DW01_add...........1

	I/O Ports
========================================
	1-bit input port...................2
	1-bit registered output port.......3
	8-bit input port...................1
	16-bit registered output port......1

---------------------------------------------------------------------------
***************************************************************************
               Date      : Fri Dec  3 17:19:04 1999
               Version   : 2000.05-SI1
               Design    : example
***************************************************************************

************************************************
*  State graph style report for process main:  *
************************************************
===========================================================================
 present  	 next
 state	input	 state		actions
---------------------------------------------------------------------------
 s_0_0	 c1	 s_1_1	 a_6	 reset_loop/busy_70 (write)
			 a_10	 reset_loop/cell_out_71 (write)
			 a_17	 reset_loop/cell_out_valid_72 (write)
			 a_22	 reset_loop/done_69 (write)
 s_1_1	 c2	 s_3_2	 a_3	 reset_loop/operational_loop/start_loop/start_78 (read)
 s_2_3	 c3	 s_2_4	 a_1	 reset_loop/operational_loop/threshold_thresh2 (read)
			 a_28	 reset_loop/operational_loop/calc_offset_89/mul_59/mult_59 (operation)
 s_2_4	 c4	 s_2_5	 a_28	 reset_loop/operational_loop/calc_offset_89/mul_59/mult_59 (operation)
 s_2_5	 c5	 s_2_6	   (masked out)
 s_2_6	 c6	 s_4_7	 a_25	 reset_loop/operational_loop/calc_offset_89/add_59/plus_59 (operation)
 s_2_6	 c7	 s_4_7	 a_58	 reset_loop/operational_loop/read_write_loop/lte_93 (operation)
 s_2_6	 c8	 s_4_7	   (masked out)
 s_2_6	 c9	 s_4_7	 a_80	 reset_loop/operational_loop/read_write_loop/MEM_READ_cell_ram_mem_read1/seq_cell_4 (operation)
 s_2_16	 c11	 s_2_17	 a_21	 reset_loop/operational_loop/done_120 (write)
 s_2_17	 c12	 s_3_2	 a_3	 reset_loop/operational_loop/start_loop/start_78 (read)
 s_3_2	 c13	 s_2_3	 a_0	 reset_loop/operational_loop/threshold_thresh1 (read)
			 a_4	 reset_loop/operational_loop/busy_84 (write)
 s_3_2	 c15	 s_3_2	 a_3	 reset_loop/operational_loop/start_loop/start_78 (read)
 s_4_7	 c17	 s_2_16	 a_5	 reset_loop/operational_loop/busy_116 (write)
			 a_20	 reset_loop/operational_loop/done_assert_done (write)
 s_4_7	 c19	 s_2_16	   (masked out)
 s_4_7	 c20	 s_2_16	   (masked out)
 s_4_7	 c21	 s_4_8	 a_2	 reset_loop/operational_loop/read_write_loop/use_thresh_offset_98 (read)
			 a_77	 reset_loop/operational_loop/read_write_loop/MEM_READ_cell_ram_mem_read2/seq_cell_1 (operation)
			 a_82	 reset_loop/operational_loop/read_write_loop/MEM_READ_cell_ram_mem_read1/seq_cell_5 (operation)
 s_4_7	 c22	 s_4_8	   (masked out)
 s_4_8	 c23	 s_4_9	 a_50	 reset_loop/operational_loop/read_write_loop/calc_offset_97/mul_59/mult_59 (operation)
			 a_79	 reset_loop/operational_loop/read_write_loop/MEM_READ_cell_ram_mem_read2/seq_cell_2 (operation)
 s_4_9	 c24	 s_4_10	 a_50	 reset_loop/operational_loop/read_write_loop/calc_offset_97/mul_59/mult_59 (operation)
 s_4_10	 c25	 s_4_11	   (masked out)
 s_4_11	 c26	 s_4_12	 a_39	 reset_loop/operational_loop/read_write_loop/add_99/plus_99 (operation)
 s_4_11	 c28	 s_4_12	 a_47	 reset_loop/operational_loop/read_write_loop/calc_offset_97/add_59/plus_59 (operation)
 s_4_12	 c29	 s_4_13	 a_39	 reset_loop/operational_loop/read_write_loop/add_99/plus_99 (operation)
 s_4_12	 c30	 s_4_13	   (masked out)
 s_4_12	 c31	 s_4_13	   (masked out)
 s_4_13	 c32	 s_4_14	 a_9	 reset_loop/operational_loop/read_write_loop/cell_out_105 (write)
			 a_16	 reset_loop/operational_loop/read_write_loop/cell_out_valid_106 (write)
 s_4_13	 c33	 s_4_14	   (masked out)
 s_4_13	 c34	 s_4_14	   (masked out)
 s_4_13	 c36	 s_4_14	   (masked out)
 s_4_14	 c37	 s_4_15	 a_15	 reset_loop/operational_loop/read_write_loop/cell_out_valid_valid0 (write)
			 a_44	 reset_loop/operational_loop/read_write_loop/add_mem_write (operation)
			 a_74	 reset_loop/operational_loop/read_write_loop/MEM_WRITE_cell_ram_mem_write/seq_cell_7 (operation)
 s_4_14	 c38	 s_4_15	   (masked out)
 s_4_15	 c39	 s_4_7	 a_58	 reset_loop/operational_loop/read_write_loop/lte_93 (operation)
 s_4_15	 c40	 s_4_7	   (masked out)
 s_4_15	 c41	 s_4_7	 a_35	 reset_loop/operational_loop/read_write_loop/add_93 (operation)
 s_4_15	 c42	 s_4_7	 a_80	 reset_loop/operational_loop/read_write_loop/MEM_READ_cell_ram_mem_read1/seq_cell_4 (operation)
 +++++	 c43	 s_0_0	 a_6	 reset_loop/busy_70 (write)
			 a_10	 reset_loop/cell_out_71 (write)
			 a_17	 reset_loop/cell_out_valid_72 (write)
			 a_22	 reset_loop/done_69 (write)
---------------------------------------------------------------------------
       ***********      Branch Conditions      ***********
---------------------------------------------------------------------------
 state	 condition	 source
---------------------------------------------------------------------------
c1        	true
c2        	true
c3        	true
c4        	true
c5        	true
c6        	true
c7        	true
c8        	true
c9        	(and (branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
		     true)
c11       	true
c12       	true
c13       	(branch 1 of conditional reset_loop/operational_loop/start_loop/SPLIT_L78)
c15       	(branch 0 of conditional reset_loop/operational_loop/start_loop/SPLIT_L78)
c17       	(branch 1 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c19       	(branch 1 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c20       	(and (branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
		     (branch 1 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93))
c21       	(and (branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
		     (not (branch 1 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)))
c22       	(not (branch 1 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93))
c23       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c24       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c25       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c26       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L98)
c28       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c29       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L98)
c30       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c31       	true
c32       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c33       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L98)
c34       	(branch 1 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L98)
c36       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c37       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c38       	true
c39       	true
c40       	true
c41       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c42       	(branch 0 of conditional reset_loop/operational_loop/read_write_loop/SPLIT_L93)
c43       	true
---------------------------------------------------------------------------
===========================================================================