example.rpt

design compile synthesis user guide

***************************************************************************
               Date      : Fri Dec  3 17:19:04 1999
               Version   : 2000.05-SI1
               Design    : example
***************************************************************************

*************************************
*  Register usage of process main:  *
*************************************

	Storage resource types
=======================
    r1457......1-bit register 
    r1703......16-bit register 
    r1754......16-bit register 
    r1765......16-bit register 
    r1792......8-bit register 
    r1796......1-bit register 
    r2909......6-bit register 
    r2912......16-bit register 



-------+-------+-------+-------+-------+-------+-------+-------+-------
 cycle | r1754 | r2912 | r1703 | r1765 | r1792 | r2909 | r1457 | r1796 
------------------------------------------------------------------------
       | (16)  | (16)  | (16)  | (16)  |  (8)  |  (6)  |  (1)  |  (1)  
========================================================================
   0   |.......|.......|.......|.......|.......|.......|.......|.......
   1   |.......|.......|.......|.......|.......|.......|..v13..|.......
   2   |.......|.......|..v6...|.......|.......|.......|.......|.......
   3   |.......|.......|..v6...|.......|..v7...|.......|.......|.......
   4   |.......|.......|..v6...|.......|..v7...|.......|.......|.......
   5   |..v0...|.......|.......|.......|.......|.......|.......|.......
   6   |.......|..v1...|.......|.......|.......|..v10..|..v11..|.......
   7   |.......|..v1...|..v5...|.......|.......|..v10..|..v11..|..v12..
   8   |.......|..v1...|..v8...|.......|..v9...|..v10..|..v11..|..v12..
   9   |.......|..v1...|..v8...|.......|..v9...|..v10..|..v11..|..v12..
  10   |..v3...|..v1...|.......|.......|.......|..v10..|..v11..|..v12..
  11   |.......|..v1...|..v2...|.......|.......|..v10..|..v11..|..v12..
  12   |.......|..v1...|..v2...|.......|.......|..v10..|..v11..|..v12..
  13   |.......|..v1...|.......|..v4...|.......|..v10..|..v11..|.......
  14   |.......|..v1...|.......|.......|.......|..v10..|..v11..|.......
  15   |.......|.......|.......|.......|.......|.......|.......|.......
  16   |.......|.......|.......|.......|.......|.......|.......|.......
  17   |.......|.......|.......|.......|.......|.......|.......|.......


	Data value name abbreviations
=======================
    v0.......16-bit data value reset_loop/operational_loop/calc_offset_89/mul_59/mult_59/Z
    v1.......16-bit data value reset_loop/operational_loop/read_write_loop/thresh_offset
    v2.......16-bit data value reset_loop/operational_loop/read_write_loop/calc_offset_97/add_59/plus_59/Z
    v3.......16-bit data value reset_loop/operational_loop/read_write_loop/calc_offset_97/mul_59/mult_59/Z
    v4.......16-bit data value reset_loop/operational_loop/read_write_loop/MEM_WRITE_cell_ram_mem_write/D
    v5.......16-bit data value reset_loop/operational_loop/read_write_loop/MEM_READ_cell_ram_mem_read1/seq_cell_5/Q
    v6.......8-bit data value reset_loop/operational_loop/threshold_thresh1/net
    v7.......8-bit data value reset_loop/operational_loop/threshold_thresh2/net
    v8.......8-bit data value reset_loop/operational_loop/read_write_loop/cell1_mem_read1/net
    v9.......8-bit data value reset_loop/operational_loop/read_write_loop/cell2_mem_read2/net
    v10......6-bit data value reset_loop/operational_loop/read_write_loop/i
    v11......1-bit data value reset_loop/operational_loop/read_write_loop/U2/Z
    v12......1-bit data value reset_loop/operational_loop/read_write_loop/U6/Z
    v13......1-bit data value reset_loop/operational_loop/start_loop/U2/Z


*****************************************
*  Operation schedule of process main:  *
*****************************************

	Resource types
=====================================
    busy.......1-bit registered output port 
    done.......1-bit registered output port 
    loop.......loop boundaries 
    p0.........16-bit registered output port cell_out
    p1.........1-bit registered output port cell_out_valid
    p2.........8-bit input port threshold
    p3.........1-bit input port use_thresh_offset
    p4.........1-bit input port start
    r25........(6_6->1)-bit DW01_cmp2 
    r38........(8_8->16)-bit DW02_mult 
    r152.......(8_8_16->16)-bit cs_rr100x50 
    r172.......(16_16->16)-bit DW01_add 
    r1444......(16->16)-bit DW01_inc 
    r1472......(7_7->8)-bit DW01_add 



                                                                         c                              
                                                                         s                              
                                                   D              D      _                              
                                    D       D      W      D       W      r                              
                                    W       W      0      W       0      r                              
                                    0       0      1      0       2      1                              
                                    1       1      _      1       _      0                              
                 p     p     p      _       _      c      _       m      0      p      p      p      p  
                 o     o     o      a       a      m      i       u      x      o      o      o      o  
                 r     r     r      d       d      p      n       l      5      r      r      r      r  
                 t     t     t      d       d      2      c       t      0      t      t      t      t  
-------+------+-----+-----+-----+-------+------+------+-------+------+------+------+------+------+------
 cycle | loop | p2  | p3  | p4  | r1472 | r172 | r25  | r1444 | r38  | r152 | busy |  p0  |  p1  | done 
---------------------------------------------------------------------------------------------------------
   0   |..L3..|.....|.....|.....|.......|......|......|.......|......|......|.W70..|.W71..|.W72..|.W69..
       |..L0..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......
   1   |.L11..|.....|.....|.R78.|.......|......|......|.......|......|......|......|......|......|......
       |..L6..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......
   2   |.L16..|.R83.|.....|.....|.......|......|......|.......|......|......|.W84..|......|......|......
       |.L15..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......
       |.L12..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......
   3   |......|.R88.|.....|.....|.......|......|......|.......|......|......|......|......|......|......
   4   |......|.....|.....|.....|.......|......|......|.......|.o59a.|......|......|......|......|......
   5   |......|.....|.....|.....|.......|......|......|.......|.o59a.|......|......|......|......|......
   6   |..L9..|.....|.....|.....|.......|......|.o93b.|..o59..|......|..oC..|......|......|......|......
   7   |.L14..|.....|.R98.|.....|.......|......|......|.......|......|..oD..|......|......|......|......
       |......|.....|.....|.....|.......|......|......|.......|......|..oA..|......|......|......|......
   8   |......|.....|.....|.....|.......|......|......|.......|......|..oB..|......|......|......|......
   9   |......|.....|.....|.....|.......|......|......|.......|.o59c.|......|......|......|......|......
  10   |......|.....|.....|.....|.......|......|......|.......|.o59c.|......|......|......|......|......
  11   |......|.....|.....|.....|.......|......|......|.o59b..|......|......|......|......|......|......
  12   |......|.....|.....|.....|.......|.o99..|......|.......|......|......|......|......|......|......
  13   |......|.....|.....|.....|.......|.o99..|......|.......|......|......|......|.W105.|.W106.|......
  14   |......|.....|.....|.....|.o93a..|......|......|.......|......|..oz..|......|......|.W110.|......
  15   |.L13..|.....|.....|.....|..o93..|......|......|.......|......|......|.W116.|......|......|.W115.
       |.L10..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......
  16   |......|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|.W120.
  17   |..L8..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......
       |..L7..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......
       |..L5..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......
       |..L4..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......
       |..L2..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......
       |..L1..|.....|.....|.....|.......|......|......|.......|......|......|......|......|......|......


	Operation name abbreviations
========================================================
    L0........loop boundaries main_design_loop_begin
    L1........loop boundaries main_design_loop_end
    L2........loop boundaries main_design_loop_cont
    L3........loop boundaries reset_loop/reset_loop_design_loop_begin
    L4........loop boundaries reset_loop/reset_loop_design_loop_end
    L5........loop boundaries reset_loop/reset_loop_design_loop_cont
    L6........loop boundaries reset_loop/operational_loop/operational_loop_design_loop_begin
    L7........loop boundaries reset_loop/operational_loop/operational_loop_design_loop_end
    L8........loop boundaries reset_loop/operational_loop/operational_loop_design_loop_cont
    L9........loop boundaries reset_loop/operational_loop/read_write_loop/read_write_loop_design_loop_begin
    L10.......loop boundaries reset_loop/operational_loop/read_write_loop/read_write_loop_design_loop_end
    L11.......loop boundaries reset_loop/operational_loop/start_loop/start_loop_design_loop_begin
    L12.......loop boundaries reset_loop/operational_loop/start_loop/start_loop_design_loop_end
    L13.......loop boundaries reset_loop/operational_loop/read_write_loop/read_write_loop_design_loop_cont
    L14.......loop boundaries reset_loop/operational_loop/read_write_loop/EXIT_L93
    L15.......loop boundaries reset_loop/operational_loop/start_loop/start_loop_design_loop_cont
    L16.......loop boundaries reset_loop/operational_loop/start_loop/EXIT_L78
    R78.......1-bit read reset_loop/operational_loop/start_loop/start_78
    R83.......8-bit read reset_loop/operational_loop/threshold_thresh1
    R88.......8-bit read reset_loop/operational_loop/threshold_thresh2
    R98.......1-bit read reset_loop/operational_loop/read_write_loop/use_thresh_offset_98
    W69.......1-bit write reset_loop/done_69
    W70.......1-bit write reset_loop/busy_70
    W71.......16-bit write reset_loop/cell_out_71
    W72.......1-bit write reset_loop/cell_out_valid_72
    W84.......1-bit write reset_loop/operational_loop/busy_84
    W105......16-bit write reset_loop/operational_loop/read_write_loop/cell_out_105
    W106......1-bit write reset_loop/operational_loop/read_write_loop/cell_out_valid_106
    W110......1-bit write reset_loop/operational_loop/read_write_loop/cell_out_valid_valid0
    W115......1-bit write reset_loop/operational_loop/done_assert_done
    W116......1-bit write reset_loop/operational_loop/busy_116
    W120......1-bit write reset_loop/operational_loop/done_120
    o59.......(16_16->16)-bit ADD_TC_OP reset_loop/operational_loop/calc_offset_89/add_59/plus_59
    o93.......(6_1->6)-bit ADD_UNS_OP reset_loop/operational_loop/read_write_loop/add_93
    o99.......(16_16->16)-bit ADD_UNS_OP reset_loop/operational_loop/read_write_loop/add_99/plus_99
    o59a......(8_8->16)-bit MULT_UNS_OP reset_loop/operational_loop/calc_offset_89/mul_59/mult_59
    o59b......(16_16->16)-bit ADD_TC_OP reset_loop/operational_loop/read_write_loop/calc_offset_97/add_59/plus_59
    o59c......(8_8->16)-bit MULT_UNS_OP reset_loop/operational_loop/read_write_loop/calc_offset_97/mul_59/mult_59
    o93a......(7_7->8)-bit ADD_UNS_OP reset_loop/operational_loop/read_write_loop/add_mem_write
    o93b......(6_6->1)-bit LEQ_UNS_OP reset_loop/operational_loop/read_write_loop/lte_93
    oA........(8_0)-bit MEM_READ_SEQ_OP_read_cs_rr100x50_state_0 reset_loop/operational_loop/read_write_loop/MEM_READ_cell_ram_mem_read2/seq_cell_1
    oB........(0->16)-bit MEM_READ_SEQ_OP_read_cs_rr100x50_state_1 reset_loop/operational_loop/read_write_loop/MEM_READ_cell_ram_mem_read2/seq_cell_2
    oC........(8_0)-bit MEM_READ_SEQ_OP_read_cs_rr100x50_state_0 reset_loop/operational_loop/read_write_loop/MEM_READ_cell_ram_mem_read1/seq_cell_4