example.vhd

design compile synthesis user guide

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY synopsys;
USE synopsys.attributes.all;


ENTITY example IS
  PORT ( clk               : IN  std_logic;
         reset             : IN  std_logic;
         start             : IN  std_logic;
         threshold         : IN  std_logic_vector(7 DOWNTO 0);
         use_thresh_offset : IN  std_logic;
         cell_out          : OUT std_logic_vector(15 DOWNTO 0);
         cell_out_valid    : OUT std_logic;
         busy              : OUT std_logic;
         done              : OUT std_logic
       );
END example;


architecture behavioral of example is

  -- behavioral vhdl attributes fix
  attribute dont_unroll : boolean;
  attribute variables   : string;
 
  TYPE ram_type IS ARRAY (199 DOWNTO 0) OF std_logic_vector(15 DOWNTO 0);

BEGIN

main : PROCESS

  VARIABLE cell : ram_type;
  CONSTANT cell_ram : resource := 0;
  ATTRIBUTE variables OF cell_ram : CONSTANT IS "cell";
  ATTRIBUTE map_to_module OF cell_ram : CONSTANT IS "cs_rr100x50";
 
  ATTRIBUTE dont_unroll OF read_write_loop : LABEL IS TRUE;


  VARIABLE cell1, cell2 : std_logic_vector(7 DOWNTO 0);
  VARIABLE cell_offset : std_logic_vector(15 DOWNTO 0);
  VARIABLE thresh1, thresh2 : std_logic_vector(7 DOWNTO 0);
  VARIABLE thresh_offset : std_logic_vector(15 DOWNTO 0);
  VARIABLE cell_value : std_logic_vector(15 DOWNTO 0);

----------------------------------------------------------------------

  FUNCTION calc_offset(
    a : std_logic_vector(7 DOWNTO 0);
    b : std_logic_vector(7 DOWNTO 0))
    RETURN std_logic_vector IS
 
    VARIABLE offset : std_logic_vector(15 DOWNTO 0);

  BEGIN
    offset := (a * b) + 1;
    RETURN offset;
  END calc_offset;

----------------------------------------------------------------------

  BEGIN
  reset_loop : LOOP

    -- Initialize outputs
    done <= '0';
    busy <= '0';
    cell_out <= "0000000000000000";
    cell_out_valid <= '0';
    WAIT UNTIL clk'event AND clk = '1';
    IF (reset = '1') THEN EXIT reset_loop; END IF;

    operational_loop : LOOP

      start_loop : WHILE (start = '0') LOOP
        WAIT UNTIL clk'event AND clk = '1';
        IF (reset = '1') THEN EXIT reset_loop; END IF;
      END LOOP; -- start_loop

      thresh1 := threshold;                    -- synopsys line_label thresh1
      busy <= '1';
      WAIT UNTIL clk'event AND clk = '1';
      IF (reset = '1') THEN EXIT reset_loop; END IF;

      thresh2 := threshold;                    -- synopsys line_label thresh2
      thresh_offset := calc_offset(thresh1, thresh2);
      WAIT UNTIL clk'event AND clk = '1';
      IF (reset = '1') THEN EXIT reset_loop; END IF;

      read_write_loop : FOR i IN 0 to 49 LOOP
        cell1 := cell(i*2)(7 DOWNTO 0);        -- synopsys line_label mem_read1
        cell2 := cell((i*2)+1)(7 DOWNTO 0);    -- synopsys line_label mem_read2

        cell_offset := calc_offset(cell1, cell2);
        IF (use_thresh_offset = '1') THEN
          cell_value := cell_offset + thresh_offset;
        ELSE
          cell_value := cell_offset;
        END IF;

        cell((i*2)+100) := cell_value;         -- synopsys line_label mem_write
        cell_out <= cell_value;
        cell_out_valid <= '1';
        WAIT UNTIL clk'event AND clk = '1';
        IF (reset = '1') THEN EXIT reset_loop; END IF;

        cell_out_valid <= '0';                 -- synopsys line_label valid0
        WAIT UNTIL clk'event AND clk = '1';
        IF (reset = '1') THEN EXIT reset_loop; END IF;
      END LOOP; -- read_write_loop

      done <= '1';                          -- synopsys line_label assert_done
      busy <= '0';
      WAIT UNTIL clk'event AND clk = '1';
      IF (reset = '1') THEN EXIT reset_loop; END IF;

      done <= '0';
      WAIT UNTIL clk'event AND clk = '1';
      IF (reset = '1') THEN EXIT reset_loop; END IF;

    END LOOP; -- operational_loop

  END LOOP; -- reset_loop

END PROCESS; -- main

END behavioral;