mult_proc.scr

design compile synthesis user guide

bc_enable_analysis_info = true

search_path = search_path + rams + hdl + db
synthetic_library = synthetic_library + cs_rams.sldb

analyze -f vhdl mult_proc.vhd
elaborate -s mult_proc

bc_time_design
write -hier -o db/mult_proc_timed.db

create_clock clk -p 20
/* bc_check_design -io cyc */

schedule -io cyc -eff med
write -hier -o db/mult_proc_sched.db
report_schedule -var -op -summ -a > reports/mult_proc.rpt