cs_rams.sl

design compile synthesis user guide

library (cs_rams.sldb) {
  module (cs_rr100x50) {
/*     
       The output of this wrapper is registered on the 
       positive edge of the clock.
       The memory core will have inverted clock. 

       Register are used in this design; Latches are avoided
       to keep this an all register design (testability).
	
	For a latch based design metheodology, this wrapper may be
	modified to use latches.

	- Hazem Almusa 7/14/95
 */

    design_library : "rams";
    parameter(addr_width) {
      formula : "max(width('ADDR'),width('ADDR'))";
      hdl_parameter : true;
    }
    parameter(data_width) {
      formula : "max(width('DATAI'),width('DATAO'))";
      hdl_parameter : true;
    }
    clocking_scheme() { 
      clock_type : positive_edge;
    }
    pin (DATAO) {
      direction : output;
      bit_width : "data_width";
      stall : active_low;
    }
    pin (ADDR1) {
      direction : input;
      bit_width : "addr_width";
      stall : active_low;
    }
    pin (ADDR2) {
      direction : input;
      bit_width : "addr_width";
      stall : active_low;
    }
    pin (DATAI) {
      direction : input;
      bit_width : "data_width";
      stall : active_low;
    }
    pin (ENABLE) {
      direction : input;
      bit_width : "1";
      stall : active_high;
    }
    pin (CLK) {  
      direction : input;
      bit_width : "1";
      clock_pin : true;
    }  
    implementation("wrap") { }
    resource (S1) {count : 2;}
    resource (S2) {}
/*     This sets up the signals for the read (address generation
       is ram setup 
 */

/*     Sample timing looks like :
       | Apply Address |  Use Data  |
*/
    binding(read) { 
      bound_operator : "MEM_READ_SEQ_OP";
      state() {
	pin_association(ADDR1) {oper_pin : ADDR;}
        pin_association(CLK) {oper_pin : CLK;}
        unbound_oper_pin(CLK) { value : "1"; }
	use_resource(S1) {}	
      }
      state() {
        pin_association(DATAO) {oper_pin : Q; stable : true;} 
        pin_association(CLK) {oper_pin : CLK;}
        unbound_oper_pin(CLK) { value : "1"; }
	use_resource(S2) {}	
      }
    }
    binding(write) {
      bound_operator : "MEM_WRITE_SEQ_OP";
/* 	 This is the write cycle : 
         The write cycle will look like 
         | GEN ADDR/DATA, WRITE INTO RAM | 
			                 | GEN ADDR/DATA, WRITE INTO RAM |
 */
      state() {
        pin_association(ADDR2) {oper_pin : ADDR;}
        pin_association(DATAI) {oper_pin : D;}
        pin_association(ENABLE) {value : "1";}
        pin_association(CLK) {oper_pin : CLK;}
        unbound_oper_pin(CLK) { value : "1"; }
        use_resource(S1) {}    
      }
    }
  }
}