example.rpt

design compile synthesis user guide

***************************************************************************
***************************************************************************
               Date      : Fri Dec  3 15:28:08 1999
               Version   : 2000.05-SI1
               Design    : example
***************************************************************************

********************************************
*  Summary report for process reset_loop:  *
********************************************
---------------------------------------------------------------------------
     Timing Summary
---------------------------------------------------------------------------
 Clock period 20.00
 Loop timing information:
    reset_loop.....................................17 cycles (cycles 0 - 17)
        operational_loop...........................16 cycles (cycles 1 - 17)
            start_loop..............................1 cycle  (cycles 1 - 2)
                (exit) EXIT_L38............................. (cycle 2)
            read_write_loop.........................9 cycles (cycles 6 - 15)
                (exit) EXIT_L49............................. (cycle 7)
---------------------------------------------------------------------------
     Area Summary
---------------------------------------------------------------------------
 Estimated combinational area    1820
 Estimated sequential area       1408
 TOTAL                           3228

 18 control states
 20 basic transitions
 4 control inputs
 28 control outputs

---------------------------------------------------------------------------
     Resource types
---------------------------------------------------------------------------
	Register Types
========================================
	1-bit register.....................2
	7-bit register.....................2
	8-bit register.....................1
	16-bit register....................4

	Operator Types
========================================
	(7_7->1)-bit DW01_cmp2.............1
	(8_7->8)-bit DW01_add..............1
	(8_8->16)-bit DW02_mult............1
	(8_8_16->16)-bit cs_rr100x50.......1
	(16->16)-bit DW01_inc..............1
	(16_16->16)-bit DW01_add...........1

	I/O Ports
========================================
	1-bit input port...................2
	1-bit registered output port.......3
	8-bit input port...................1
	16-bit registered output port......1

---------------------------------------------------------------------------
***************************************************************************
               Date      : Fri Dec  3 15:28:08 1999
               Version   : 2000.05-SI1
               Design    : example
***************************************************************************

******************************************************
*  State graph style report for process reset_loop:  *
******************************************************
===========================================================================
 present  	 next
 state	input	 state		actions
---------------------------------------------------------------------------
 s_0_0	 c1	 s_0_1	 a_6	 busy_31 (write)
			 a_10	 cell_out_32 (write)
			 a_17	 cell_out_valid_33 (write)
			 a_22	 done_30 (write)
 s_0_1	 c2	 s_2_2	 a_3	 operational_loop/start_loop/start_38 (read)
 s_1_3	 c3	 s_1_4	 a_1	 operational_loop/threshold_thresh2 (read)
			 a_28	 operational_loop/calc_offset_46/mul_81 (operation)
 s_1_4	 c4	 s_1_5	 a_28	 operational_loop/calc_offset_46/mul_81 (operation)
 s_1_5	 c5	 s_1_6	   (masked out)
 s_1_6	 c6	 s_3_7	 a_25	 operational_loop/calc_offset_46/add_81 (operation)
 s_1_6	 c7	 s_3_7	 a_62	 operational_loop/read_write_loop/lte_49 (operation)
 s_1_6	 c8	 s_3_7	 a_80	 operational_loop/read_write_loop/cell_read_mem_read1/seq_cell_1 (operation)
 s_1_6	 c10	 s_3_7	   (masked out)
 s_1_16	 c11	 s_1_17	 a_21	 operational_loop/done_70 (write)
 s_1_17	 c12	 s_2_2	 a_3	 operational_loop/start_loop/start_38 (read)
 s_2_2	 c13	 s_1_3	 a_0	 operational_loop/threshold_thresh1 (read)
			 a_5	 operational_loop/busy_43 (write)
 s_2_2	 c15	 s_2_2	 a_3	 operational_loop/start_loop/start_38 (read)
 s_3_7	 c17	 s_1_16	 a_4	 operational_loop/busy_68 (write)
			 a_20	 operational_loop/done_assert_done (write)
 s_3_7	 c19	 s_1_16	   (masked out)
 s_3_7	 c20	 s_1_16	   (masked out)
 s_3_7	 c21	 s_3_8	 a_2	 operational_loop/read_write_loop/use_thresh_offset_54 (read)
			 a_44	 operational_loop/read_write_loop/add_mem_read2 (operation)
			 a_77	 operational_loop/read_write_loop/cell_read_mem_read2/seq_cell_4 (operation)
			 a_82	 operational_loop/read_write_loop/cell_read_mem_read1/seq_cell_2 (operation)
 s_3_7	 c22	 s_3_8	   (masked out)
 s_3_8	 c23	 s_3_9	 a_35	 operational_loop/read_write_loop/add_49 (operation)
 s_3_8	 c24	 s_3_9	 a_55	 operational_loop/read_write_loop/calc_offset_53/mul_81 (operation)
			 a_79	 operational_loop/read_write_loop/cell_read_mem_read2/seq_cell_5 (operation)
 s_3_8	 c25	 s_3_9	   (masked out)
 s_3_9	 c26	 s_3_10	 a_55	 operational_loop/read_write_loop/calc_offset_53/mul_81 (operation)
 s_3_10	 c27	 s_3_11	   (masked out)
 s_3_11	 c28	 s_3_12	 a_39	 operational_loop/read_write_loop/add_55 (operation)
 s_3_11	 c30	 s_3_12	 a_52	 operational_loop/read_write_loop/calc_offset_53/add_81 (operation)
 s_3_11	 c31	 s_3_12	   (masked out)
 s_3_12	 c33	 s_3_13	 a_39	 operational_loop/read_write_loop/add_55 (operation)
 s_3_12	 c34	 s_3_13	   (masked out)
 s_3_12	 c35	 s_3_13	   (masked out)
 s_3_12	 c36	 s_3_13	   (masked out)
 s_3_13	 c37	 s_3_14	 a_9	 operational_loop/read_write_loop/cell_out_60 (write)
			 a_16	 operational_loop/read_write_loop/cell_out_valid_61 (write)
 s_3_13	 c38	 s_3_14	   (masked out)
 s_3_13	 c39	 s_3_14	   (masked out)
 s_3_14	 c40	 s_3_15	 a_15	 operational_loop/read_write_loop/cell_out_valid_valid0 (write)
			 a_48	 operational_loop/read_write_loop/add_mem_write (operation)
			 a_74	 operational_loop/read_write_loop/cell_write_mem_write/seq_cell_7 (operation)
 s_3_14	 c41	 s_3_15	   (masked out)
 s_3_15	 c42	 s_3_7	 a_62	 operational_loop/read_write_loop/lte_49 (operation)
 s_3_15	 c43	 s_3_7	   (masked out)
 s_3_15	 c44	 s_3_7	   (masked out)
 s_3_15	 c45	 s_3_7	 a_80	 operational_loop/read_write_loop/cell_read_mem_read1/seq_cell_1 (operation)
 +++++	 c46	 s_0_0	 a_6	 busy_31 (write)
			 a_10	 cell_out_32 (write)
			 a_17	 cell_out_valid_33 (write)
			 a_22	 done_30 (write)
---------------------------------------------------------------------------
       ***********      Branch Conditions      ***********
---------------------------------------------------------------------------
 state	 condition	 source
---------------------------------------------------------------------------
c1        	true
c2        	true
c3        	true
c4        	true
c5        	true
c6        	true
c7        	true
c8        	(and (branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
		     true)
c10       	true
c11       	true
c12       	true
c13       	(branch 1 of conditional operational_loop/start_loop/SPLIT_L38)
c15       	(branch 0 of conditional operational_loop/start_loop/SPLIT_L38)
c17       	(branch 1 of conditional operational_loop/read_write_loop/SPLIT_L49)
c19       	(and (branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
		     (branch 1 of conditional operational_loop/read_write_loop/SPLIT_L49))
c20       	(branch 1 of conditional operational_loop/read_write_loop/SPLIT_L49)
c21       	(and (branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
		     (not (branch 1 of conditional operational_loop/read_write_loop/SPLIT_L49)))
c22       	(not (branch 1 of conditional operational_loop/read_write_loop/SPLIT_L49))
c23       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
c24       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
c25       	true
c26       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
c27       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
c28       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L54)
c30       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
c31       	(branch 1 of conditional operational_loop/read_write_loop/SPLIT_L54)
c33       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L54)
c34       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
c35       	(branch 1 of conditional operational_loop/read_write_loop/SPLIT_L54)
c36       	true
c37       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
c38       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L54)
c39       	(branch 1 of conditional operational_loop/read_write_loop/SPLIT_L54)
c40       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
c41       	true
c42       	true
c43       	true
c44       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
c45       	(branch 0 of conditional operational_loop/read_write_loop/SPLIT_L49)
c46       	true
---------------------------------------------------------------------------
===========================================================================