example.scr

来自「design compile synthesis user guide」· SCR 代码 · 共 16 行

bc_enable_analysis_info = true

search_path = search_path + rams + hdl + db
synthetic_library = synthetic_library + cs_rams.sldb

analyze -f verilog example.v
elaborate -s example

bc_time_design

create_clock clk -p 20
schedule -io su -eff med
write -hier -o db/example.db
report_schedule -var -op -summ -a > reports/example.rpt