example.proj

来自「design compile synthesis user guide」· PROJ 代码 · 共 32 行

set search_path " \
                     . \
                     ./vhdl \
                     ./hdl \
                     ./sl \
                     ./sldb \
                     $SYNOPSYS/libraries/syn \
                     $SYNOPSYS/dw/sim_ver \
                     hdl \
                     db \
                     rams \
                     ./work \
                     $SYNOPSYS/dw/dw01/lib \
                     $SYNOPSYS/dw/dw02/lib \
                     $SYNOPSYS/dw/dw03/lib \
                     $SYNOPSYS/dw/dw04/lib \
                     $SYNOPSYS/dw/dw06/lib \
                     $SYNOPSYS/dw/dw07/lib \
                     $SYNOPSYS/dw/dw08/lib \
                     $SYNOPSYS/packages/dware/lib \
                     $SYNOPSYS/packages/gscomp/lib \
                     $SYNOPSYS/packages/gtech/lib \
                     $SYNOPSYS/packages/IEEE/lib \
                     $SYNOPSYS/packages/IEEE_asic/lib \
                     $SYNOPSYS/packages/synopsys/lib \
                     $SYNOPSYS/packages/VITAL/lib \
                   "
set top_design_name " example "
set gtech_top_db_file " example.db "