top_timing.rpt

design compile synthesis user guide

Information: Updating design information... (UID-85)
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : top
Version: 2000.05-1
Date   : Thu Jul 13 16:29:50 2000
****************************************

Operating Conditions: 
Wire Load Model Mode: top

  Startpoint: fsm/CURRSTATE_reg[3]
              (rising edge-triggered flip-flop clocked by vclock)
  Endpoint: DOUT[8] (output port clocked by vclock)
  Path Group: vclock
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  top                10x10                 class

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock vclock (rise edge)                                0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  fsm/CURRSTATE_reg[3]/CP (FD2S)                          0.00       0.00 r
  fsm/CURRSTATE_reg[3]/QN (FD2S)                          1.82       1.82 f
  fsm/U485/Z (ND2I)                                       0.31       2.13 r
  fsm/U460/Z (IVI)                                        0.18       2.31 f
  fsm/U517/Z (ND4P)                                       0.83       3.14 r
  fsm/U483/Z (ND2I)                                       0.30       3.44 f
  fsm/ENABLE_SELECT[0] (addr_fsm)                         0.00       3.44 f
  combo/ENABLE_SELECT[0] (addr_combo)                     0.00       3.44 f
  combo/U519/Z (ND2I)                                     0.26       3.70 r
  combo/U520/Z (IVI)                                      0.13       3.83 f
  combo/U700/Z (ND2I)                                     0.34       4.17 r
  combo/U532/Z (MUX21LP)                                  1.06       5.23 r
  combo/datapath_66/sub_46/minus/minus/B[0] (addr_combo_DW01_sub_8_0)
                                                          0.00       5.23 r
  combo/datapath_66/sub_46/minus/minus/U13/Z (MUX21L)     0.93       6.16 r
  combo/datapath_66/sub_46/minus/minus/U1/U9_1_1_3/Z (MUX21LP)
                                                          1.00       7.16 r
  combo/datapath_66/sub_46/minus/minus/U26/Z (IVI)        0.18       7.34 f
  combo/datapath_66/sub_46/minus/minus/U1/U5_2_6/Z (MUX21LP)
                                                          1.04       8.38 r
  combo/datapath_66/sub_46/minus/minus/DIFF[6] (addr_combo_DW01_sub_8_0)
                                                          0.00       8.38 r
  combo/datapath_66/sub_48/minus/minus/B[6] (addr_combo_DW01_sub_11_0)
                                                          0.00       8.38 r
  combo/datapath_66/sub_48/minus/minus/U13/Z (IVI)        0.13       8.51 f
  combo/datapath_66/sub_48/minus/minus/U1/U1_1_6/Z (ND2I)
                                                          0.34       8.86 r
  combo/datapath_66/sub_48/minus/minus/U1/U6_1_0_7/Z (MUX21LP)
                                                          1.02       9.88 r
  combo/datapath_66/sub_48/minus/minus/U1/U6_1_1_7/Z (MUX21L)
                                                          0.50      10.38 f
  combo/datapath_66/sub_48/minus/minus/U1/U5_2_7/Z (MUX21LP)
                                                          0.55      10.93 r
  combo/datapath_66/sub_48/minus/minus/DIFF[7] (addr_combo_DW01_sub_11_0)
                                                          0.00      10.93 r
  combo/U651/Z (NR2I)                                     0.21      11.14 f
  combo/U515/Z (AN2I)                                     0.64      11.78 f
  combo/U521/Z (ND2I)                                     0.26      12.04 r
  combo/U544/Z (ND2I)                                     0.13      12.17 f
  combo/U699/Z (IVI)                                      0.31      12.48 r
  combo/datapath_66/add_72/plus/plus/B[1] (addr_combo_DW01_add_11_1)
                                                          0.00      12.48 r
  combo/datapath_66/add_72/plus/plus/U18/Z (ND2I)         0.30      12.78 f
  combo/datapath_66/add_72/plus/plus/U25/Z (NR2I)         0.75      13.53 r
  combo/datapath_66/add_72/plus/plus/U1_4_1_2/Z (AO6P)
                                                          0.29      13.82 f
  combo/datapath_66/add_72/plus/plus/U1_4_2_6/Z (AO7P)
                                                          1.22      15.04 r
  combo/datapath_66/add_72/plus/plus/U43/Z (ND2I)         0.13      15.17 f
  combo/datapath_66/add_72/plus/plus/U0_5_8/Z (ENI)       0.36      15.53 r
  combo/datapath_66/add_72/plus/plus/SUM[8] (addr_combo_DW01_add_11_1)
                                                          0.00      15.53 r
  combo/U514/Z (ND2I)                                     0.13      15.66 f
  combo/U674/Z (ND2I)                                     0.26      15.92 r
  combo/U675/Z (IVI)                                      0.13      16.05 f
  combo/DOUT_tri[8]/Z (BTS5)                              0.97      17.02 r
  combo/DOUT[8] (addr_combo)                              0.00      17.02 r
  DOUT[8] (out)                                           0.00      17.02 r
  data arrival time                                                 17.02

  clock vclock (rise edge)                               10.00      10.00
  clock network delay (ideal)                             0.00      10.00
  output external delay                                  -0.30       9.70
  data required time                                                 9.70
  --------------------------------------------------------------------------
  data required time                                                 9.70
  data arrival time                                                -17.02
  --------------------------------------------------------------------------
  slack (VIOLATED)                                                  -7.32