addr_fsm_rtl.vhd

design compile synthesis user guide

---------------------------------------------------------------
-- FSM block for RTL Analyzer tutorial
---------------------------------------------------------------
-- Revision 1.3  1998/06/08  dannyb
-- format
--
-- Revision 1.2  1997/03/05  baldrik
-- add RCS stuff
--
-- Revision 1.1  1997/02/08  baldrik
-- Initial revision
---------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;

architecture rtl of addr_fsm is

  type STATE is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9);

  signal INTEN, INTCSO, INTCS : std_logic_vector(2 downto 0);
  signal BUSACK               : std_logic;
  signal CURRSTATE, NEXTSTATE : STATE;

begin

   INTCSO     <= INTEN or (AS,AS,AS);
   BUS_ENABLE <= BUSACK or and_reduce(INTCSO);
   CS         <= INTCS or (AS,AS,AS);


   process (ADDR)
   begin
     if (ADDR(15) = '1') then
       INTEN <= "011";
     elsif (ADDR(11) = '1') then
       INTEN <= "101";
     elsif (ADDR(7) = '1') then
       INTEN <= "110";
     else
       INTEN <= "111";
     end if;
   end process;

   STATE_CLOCK: process (RST, CLK)
   begin
     if (RST = '0') then
	CURRSTATE <= s0;
     elsif (CLK'event and CLK = '1') then
	CURRSTATE <= NEXTSTATE;
     end if;
   end process STATE_CLOCK;


   FSM: process(CURRSTATE, AS, INTCSO, BREQ)
   begin
      ENABLE_SELECT <= "000";
      INTCS <= "111";
      BUSACK <= '1';
      NEXTSTATE <= CURRSTATE;
      case CURRSTATE is
	when s0 =>
	  INTCS <= "111"; BUSACK <= '1';
	  if (BREQ = '1') then
	    ENABLE_SELECT <= "001";
	    NEXTSTATE <= s3;
	  elsif (INTCSO(2) = '0') then
	    ENABLE_SELECT <= "010";
	    NEXTSTATE <= s1;
	  elsif (INTCSO(1) = '0') then
	    ENABLE_SELECT <= "100";
	    NEXTSTATE <= s2;
	  elsif (INTCSO(0) = '0') then
	    ENABLE_SELECT <= "111";
	    NEXTSTATE <= s4;
	  else 
	    ENABLE_SELECT <= "000";
	    NEXTSTATE <= s0;
	  end if;
	when s1 =>
	  INTCS(2) <= '0';
	  NEXTSTATE  <= s5;
	when s5 =>
	  INTCS(2) <= '0';
	  NEXTSTATE <= s6;
	when s6 =>
	  INTCS(2) <= '0';
	  NEXTSTATE <= s7;
	when s7 =>
	  INTCS(2) <= '0';
	  if (AS = '1') then 
	    NEXTSTATE <= s0;
	  end if;
	when s2 =>
	  NEXTSTATE <= s9;
	when s9 =>
	  INTCS(1) <= '0';
	  if (AS = '1') then 
	    NEXTSTATE <= s0;
	  end if;
	when s3 =>
	  BUSACK <= '1';
	  if (BREQ = '0') then 
	    NEXTSTATE <= s8;
	  end if;
	when s8 =>
	  BUSACK <= '0';
	  NEXTSTATE <= s0;
	when s4 =>
	  INTCS(0) <= '0';
	  if (AS = '1') then 
	    NEXTSTATE <= s0;
	  end if;
	when others =>
	  NEXTSTATE <= s0;
      end case;
   end process FSM;

end rtl;