top_rtl.vhd

design compile synthesis user guide

---------------------------------------------------------------
-- Top level entity for RTL Analyzer tutorial
---------------------------------------------------------------
-- Revision 1.4  1998/06/08  dannyb
-- format
--
-- Revision 1.3  1997/03/06  baldrik
-- constanted wrong signal
--
-- Revision 1.2  1997/03/06  baldrik
-- use datatypes
--
-- Revision 1.1  1997/03/05  baldrik
-- Initial revision
---------------------------------------------------------------

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

library WORK;
use WORK.DATAPATH.ADDR_TYPE;
use WORK.DATAPATH.POINT_TYPE;

architecture rtl of top is

signal  ENABLE_SELECT : std_logic_vector(2 downto 0);
signal  CS            : std_logic_vector(2 downto 0);
signal  SELECT_FE_L   : std_logic;
signal  WR_FE_L       : std_logic;
signal  BUS_ENABLE    : std_logic;

-------------------------------------------------------

component addr_combo
  port(BASE          : in std_logic_vector(19 downto 0); 
       INST_OFFSET   : in ADDR_TYPE;  
       READ_OFFSET   : in ADDR_TYPE;
       WRITE_OFFSET  : in ADDR_TYPE;
       ADDR          : in ADDR_TYPE;
       READ_POINTER  : in POINT_TYPE;
       WRITE_POINTER : in POINT_TYPE;
       ENABLE_SELECT : in std_logic_vector(2 downto 0);
       BUS_ENABLE    : in std_logic;
       DOUT_SELECT   : in std_logic;
       DOUT          : out std_logic_vector(31 downto 0)
      );
end component;
-------------------------------------------------------

component addr_fsm
  port(RST           : in  std_logic;
       CLK           : in  std_logic;
       AS            : in  std_logic;
       BREQ          : in  std_logic;
       ADDR          : in  ADDR_TYPE;
       CS            : out std_logic_vector(2 downto 0);
       ENABLE_SELECT : out std_logic_vector(2 downto 0);
       BUS_ENABLE    : out std_logic
      );
end component;
-------------------------------------------------------

begin

  fsm : addr_fsm port map(
    CLK           => CLK,
    RST           => RST,
    AS            => AS,        
    BREQ          => BREQ,
    ADDR          => ADDR, 
    CS            => CS, 
    ENABLE_SELECT => ENABLE_SELECT,
    BUS_ENABLE    => BUS_ENABLE
  );
  
  combo: addr_combo port map(
    BASE          => BASE,
    INST_OFFSET   => INST_OFFSET,
    READ_OFFSET   => READ_OFFSET,
    WRITE_OFFSET  => WRITE_OFFSET,
    ADDR          => ADDR,
    READ_POINTER  => READ_POINTER,
    WRITE_POINTER => WRITE_POINTER,
    ENABLE_SELECT => ENABLE_SELECT,
    DOUT_SELECT   => DOUT_SELECT,
    BUS_ENABLE    => BUS_ENABLE,
    DOUT          => DOUT
  );

  SELECT_FE_L <= '1'; -- for future expansion
  WR_FE_L <= '1';  -- for future expansion
  
  chipsel: process(CS, ADR_PT)
  begin
    for i in 2 downto 0 loop
      ADR(i) <= CS(i) or ADR_PT(i);
    end loop;
    
  end process chipsel;
  
  SELECT_L <= SELECT_FE_L and SELECT_PT_L;
  WR_L <= WR_FE_L and WR_PT_L;

end rtl;