addr_combo.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 35 行

-----------------------------------------------------------------
-- Combinational address block entity for RTL Analyzer tutorial
-- dependant on DATAPATH package
-----------------------------------------------------------------
-- Revision 1.3  1998/06/08  dannyb
-- format
--
-- Revision 1.2  1997/03/06  baldrik
-- use datatypes
--
-- Revision 1.1  1997/03/05  baldrik
-- format
-----------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.DATAPATH.ADDR_TYPE;
use WORK.DATAPATH.POINT_TYPE;

entity addr_combo is
  port(BASE          : in std_logic_vector(19 downto 0); 
       INST_OFFSET   : in ADDR_TYPE;  
       READ_OFFSET   : in ADDR_TYPE;
       WRITE_OFFSET  : in ADDR_TYPE;
       ADDR          : in ADDR_TYPE;
       READ_POINTER  : in POINT_TYPE;
       WRITE_POINTER : in POINT_TYPE;
       ENABLE_SELECT : in std_logic_vector(2 downto 0);
       BUS_ENABLE    : in std_logic;
       DOUT_SELECT   : in std_logic;
       DOUT          : out std_logic_vector(31 downto 0)
      );
end addr_combo;