addr_fsm.vhd

design compile synthesis user guide

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-- FSM block entity for RTL Analyzer tutorial
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-- Revision 1.3  1998/06/08  dannyb
-- format
--
-- Revision 1.2  1997/03/05  baldrik
-- add RCS stuff
--
-- Revision 1.1  1997/02/08  baldrik
-- Initial revision
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library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.DATAPATH.ADDR_TYPE;

entity addr_fsm is
  port(RST           : in  std_logic;
       CLK           : in  std_logic;
       AS            : in  std_logic;
       BREQ          : in  std_logic;
       ADDR          : in  ADDR_TYPE;
       CS            : out std_logic_vector(2 downto 0);
       ENABLE_SELECT : out std_logic_vector(2 downto 0);
       BUS_ENABLE    : out std_logic
      );
end addr_fsm;