top.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 42 行

---------------------------------------------------------------
-- Top level entity for RTL Analyzer tutorial
---------------------------------------------------------------
-- Revision 1.3  1998/06/08  dannyb
-- format
--
-- Revision 1.2  1997/03/06  baldrik
-- use datatypes
--
-- Revision 1.1  1997/03/05  baldrik
-- Initial revision
---------------------------------------------------------------

Library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.DATAPATH.ADDR_TYPE;
use WORK.DATAPATH.POINT_TYPE;

entity top is
  port(CLK           : in     std_logic;
       RST           : in     std_logic;
       BASE          : in     std_logic_vector(19 downto 0); 
       INST_OFFSET   : in     ADDR_TYPE;  
       READ_OFFSET   : in     ADDR_TYPE;
       WRITE_OFFSET  : in     ADDR_TYPE;
       ADDR          : in     ADDR_TYPE;
       READ_POINTER  : in     POINT_TYPE;
       WRITE_POINTER : in     POINT_TYPE;
       AS            : in     std_logic;
       BREQ          : in     std_logic;
       ADR_PT        : in     std_logic_vector(2 downto 0);
       SELECT_PT_L   : in     std_logic;
       WR_PT_L       : in     std_logic;
       DOUT_SELECT   : in     std_logic;
       DOUT          : out    std_logic_vector(31 downto 0);
       ADR           : buffer std_logic_vector(2 downto 0);
       SELECT_L      : buffer std_logic;
       WR_L          : buffer std_logic
      );
end top;