constraints.scr

design compile synthesis user guide

/*************************************************************/
/*  Script to apply constraints to the tutorial design.      */
/*                                                           */
/*************************************************************/

period = 10.0; 		/* 10nS clock */
def_ip_delay = 0.1; 	/* default input delay */
def_op_delay = 0.3; 	/* default output delay */
late_delay   = 8.0; 	/* delay for late signals */
impossible_delay  = 9.8; /* delay for very late signals */

/* define input groups (used to apply the constraints */
clocks = {"CLK"};
late_inputs = find("port", "*OFFSET*");
sync_inputs = all_inputs() 	- find("port", clocks) \
				- find("port", "RST") \
  				- late_inputs;
  				
sync_outputs = all_outputs() 	- find("port", clocks);

create_clock find("port", clocks ) 	-name vclock \
					-period period;

/* apply the constraints to the input groups */
set_input_delay def_ip_delay -clock vclock sync_inputs;

set_input_delay def_ip_delay -clock vclock late_inputs;

/* apply the constraints to the output groups */

set_output_delay def_op_delay -clock vclock sync_outputs;

/*************************************************************/
/* Uncomment the following 3 set_input delay commands to     */
/* see how late arriving inputs can affect LL/C              */
/*************************************************************/
/*
set_input_delay late_delay -clock vclock READ_OFFSET; 
set_input_delay late_delay -clock vclock WRITE_OFFSET; 
set_input_delay impossible_delay -clock vclock INST_OFFSET; 
*/

/* end of constraints file */