top_timing.rpt

design compile synthesis user guide

Information: Updating design information... (UID-85)
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : top
Version: 2000.05-1
Date   : Thu Jul 13 16:32:59 2000
****************************************

Operating Conditions: 
Wire Load Model Mode: top

  Startpoint: fsm/CURRSTATE_reg[0]
              (rising edge-triggered flip-flop clocked by vclock)
  Endpoint: DOUT[8] (output port clocked by vclock)
  Path Group: vclock
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  top                10x10                 class

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock vclock (rise edge)                                0.00       0.00
  clock network delay (ideal)                             0.00       0.00
  fsm/CURRSTATE_reg[0]/CP (FD2)                           0.00       0.00 r
  fsm/CURRSTATE_reg[0]/Q (FD2)                            1.59       1.59 f
  fsm/U364/Z (NR2I)                                       0.59       2.18 r
  fsm/U323/Z (ND2I)                                       0.13       2.31 f
  fsm/U324/Z (IVI)                                        0.31       2.62 r
  fsm/U332/Z (ND2I)                                       0.30       2.92 f
  fsm/U345/Z (ND2I)                                       0.36       3.27 r
  fsm/ENABLE_SELECT[0] (addr_fsm)                         0.00       3.27 r
  combo/ENABLE_SELECT[0] (addr_combo)                     0.00       3.27 r
  combo/U181/Z (ND2I)                                     0.13       3.40 f
  combo/U182/Z (IVI)                                      0.31       3.71 r
  combo/U346/Z (ND2I)                                     0.30       4.01 f
  combo/U144/Z (IVI)                                      0.29       4.30 r
  combo/U298/Z (MUX21L)                                   0.65       4.95 f
  combo/datapath_50/datapath_50/sub_80/B[4] (addr_combo_DW01_sub_8_2)
                                                          0.00       4.95 f
  combo/datapath_50/datapath_50/sub_80/U47/Z (IVI)        0.36       5.32 r
  combo/datapath_50/datapath_50/sub_80/U29/Z (ND2I)       0.22       5.53 f
  combo/datapath_50/datapath_50/sub_80/U42/Z (NR2I)       0.59       6.13 r
  combo/datapath_50/datapath_50/sub_80/U25/Z (ND2I)       0.13       6.26 f
  combo/datapath_50/datapath_50/sub_80/U23/Z (IVI)        0.25       6.50 r
  combo/datapath_50/datapath_50/sub_80/U53/Z (ENI)        0.55       7.05 f
  combo/datapath_50/datapath_50/sub_80/DIFF[5] (addr_combo_DW01_sub_8_2)
                                                          0.00       7.05 f
  combo/datapath_50/datapath_50/sub_82/B[5] (addr_combo_DW01_sub_11_0)
                                                          0.00       7.05 f
  combo/datapath_50/datapath_50/sub_82/U64/Z (IVI)        0.42       7.47 r
  combo/datapath_50/datapath_50/sub_82/U1/U1_1_5/Z (ND2I)
                                                          0.20       7.67 f
  combo/datapath_50/datapath_50/sub_82/U1/U10_2_0_5/Z (MUX21LP)
                                                          0.63       8.30 r
  combo/datapath_50/datapath_50/sub_82/U68/Z (IVI)        0.18       8.48 f
  combo/datapath_50/datapath_50/sub_82/U1/U6_2_1_6/Z (MUX21L)
                                                          0.93       9.41 r
  combo/datapath_50/datapath_50/sub_82/U1/U5_2_6/Z (MUX21LP)
                                                          0.49       9.90 f
  combo/datapath_50/datapath_50/sub_82/DIFF[6] (addr_combo_DW01_sub_11_0)
                                                          0.00       9.90 f
  combo/U312/Z (ND3P)                                     0.74      10.64 r
  combo/U313/Z (NR2I)                                     0.21      10.85 f
  combo/U232/Z (ND2I)                                     0.36      11.20 r
  combo/U375/Z (IVI)                                      0.20      11.40 f
  combo/datapath_50/datapath_50/add_101/B[1] (addr_combo_DW01_add_11_2)
                                                          0.00      11.40 f
  combo/datapath_50/datapath_50/add_101/U0_1_1/Z (ND2I)
                                                          0.26      11.66 r
  combo/datapath_50/datapath_50/add_101/U1_2_0_1/Z (IVI)
                                                          0.20      11.86 f
  combo/datapath_50/datapath_50/add_101/U30/Z (ND2I)      0.26      12.12 r
  combo/datapath_50/datapath_50/add_101/U31/Z (IVI)       0.18      12.30 f
  combo/datapath_50/datapath_50/add_101/U15/Z (AO6P)      1.31      13.61 r
  combo/datapath_50/datapath_50/add_101/U1_4_2_6/Z (AO7P)
                                                          0.52      14.13 f
  combo/datapath_50/datapath_50/add_101/U34/Z (ND2I)      0.26      14.39 r
  combo/datapath_50/datapath_50/add_101/U0_5_8/Z (ENI)
                                                          0.43      14.82 f
  combo/datapath_50/datapath_50/add_101/SUM[8] (addr_combo_DW01_add_11_2)
                                                          0.00      14.82 f
  combo/U304/Z (IVI)                                      0.29      15.11 r
  combo/U183/Z (MUX21L)                                   0.45      15.56 f
  combo/U233/Z (ND2I)                                     0.26      15.82 r
  combo/DOUT_tri[8]/Z (BTS5)                              0.69      16.51 f
  combo/DOUT[8] (addr_combo)                              0.00      16.51 f
  DOUT[8] (out)                                           0.00      16.51 f
  data arrival time                                                 16.51

  clock vclock (rise edge)                               10.00      10.00
  clock network delay (ideal)                             0.00      10.00
  output external delay                                  -0.30       9.70
  data required time                                                 9.70
  --------------------------------------------------------------------------
  data required time                                                 9.70
  data arrival time                                                -16.51
  --------------------------------------------------------------------------
  slack (VIOLATED)                                                  -6.81