top.v

design compile synthesis user guide

//*************************************************************
//  Top Level file for RTL Analyzer Tutorial
//*************************************************************
//
// Revision 1.1  1998/06/08  dannyb
// format
//*************************************************************

`timescale 1ns/10ps

module top ( CLK, RST, BASE, INST_OFFSET, READ_OFFSET, WRITE_OFFSET, ADDR,
    READ_POINTER, WRITE_POINTER, AS, BREQ, ADR_PT, SELECT_PT_L, WR_PT_L, 
    DOUT_SELECT, DOUT, ADR, SELECT_L, WR_L ) ;
    input CLK ;
    input RST ;
    input [19:0] BASE ;
    input [15:0] INST_OFFSET ;
    input [15:0] READ_OFFSET ;
    input [15:0] WRITE_OFFSET ;
    input [15:0] ADDR ;
    input [7:0] READ_POINTER ;
    input [7:0] WRITE_POINTER ;
    input AS ;
    input BREQ ;
    input [2:0] ADR_PT ;
    input SELECT_PT_L ;
    input WR_PT_L ;
    input DOUT_SELECT ;
    output [31:0] DOUT ;
    output [2:0] ADR;
    output SELECT_L ;
    output WR_L ;

    reg [31:0] DOUT ;
    reg [2:0] ENABLE_SELECT ;
    reg [2:0] CS;
    wire SELECT_FE_L = 'b1 ;
    wire WR_FE_L = 'b1; 
    reg BUS_ENABLE ;
    reg [2:0] ADR ;
    reg SELECT_L ;
    reg WR_L ;

   addr_fsm fsm ( .CLK ( CLK ), 
                  .RST ( RST ), 
                  .AS ( AS), 
                  .BREQ ( BREQ ),
                  .ADDR ( ADDR ), 
                  .CS ( CS ), 
                  .ENABLE_SELECT ( ENABLE_SELECT ), 
                  .BUS_ENABLE ( BUS_ENABLE )
                );

   addr_combo combo ( .BASE ( BASE ), 
                      .INST_OFFSET ( INST_OFFSET ),
                      .READ_OFFSET ( READ_OFFSET ), 
                      .WRITE_OFFSET ( WRITE_OFFSET ), 
                      .ADDR ( ADDR ), 
                      .READ_POINTER ( READ_POINTER ),
                      .WRITE_POINTER ( WRITE_POINTER ), 
                      .ENABLE_SELECT ( ENABLE_SELECT ), 
                      .DOUT_SELECT ( DOUT_SELECT ), 
                      .BUS_ENABLE ( BUS_ENABLE ),
                      .DOUT ( DOUT ) 
                    );

  always @ (CS or ADR_PT or SELECT_FE_L or SELECT_PT_L or WR_FE_L or WR_PT_L )
  begin: process
    integer i;
    ADR[0] = CS[0] | ADR_PT[0];
    for (i=2; i>=0; i=i-1) 
      ADR[i] = CS[i] | ADR_PT[i];

    SELECT_L = SELECT_FE_L & SELECT_PT_L;
    WR_L = WR_FE_L & WR_PT_L;
  end

endmodule //top